El-Bay Bourennane

A UML and Colored Petri Nets Integrated Modeling and Analysis Approach using Graph Transformation

Nowadays, UML is considered to be the standardized language for object-oriented modeling and analysis. However, UML cannot be used for automatic analyses and simulation. In this paper, we propose an approach for transforming UML statechart and collaboration diagrams to Colored Petri net models. This transformation aims to bridge the gap between informal notation (UML diagrams) and more formal notation (Colored Petri net models) for analysis purposes. It produces highly- structured, graphical, and rigorously-analyzable models that facilitate early detection of errors such as deadlock and livelock. The approach is based on graph transformations where the input and output of the transformation process are graphs. The meta-modeling tool AToM3 is used. A case study is presented to illustrate our approach.

Generalization of Canny---Deriche filter for detection of noisy exponential edge

This paper presents a generalization of the Canny-Deriche filter for ramp edge detection with optimization criteria used by Canny (signal-to-noise ratio, localization, and suppression of false responses). Using techniques similar to those developed by Deriche, we derive a filter which maximizes the product of the first two criteria under the constraint of the last one. The result is an infinite length impulse response filter which leads to a stable third-order recursive implementation. Its performance shows an increase of the signal-to-noise ratio in the case of blurred and noisy images, compared to the results obtained from Deriches filter.

Automatic hardware implementation tool for a discrete Adaboost-based decision algorithm

We propose a method and a tool for automatic generation of hardware implementation of a decision rule based on the Adaboost algorithm. We review the principles of the classification method and we evaluate its hardware implementation cost in terms of FPGAs slice, using different weak classifiers based on the general concept of hyperrectangle. The main novelty of our approach is that the tool allows the user to find automatically an appropriate tradeoff between classification performances and hardware implementation cost, and that the generated architecture is optimized for each training process. We present results obtained using Gaussian distributions and examples from UCI databases. Finally, we present an example of industrial application of real-time textured image segmentation.

TLM Platform Based on SystemC for STARSoC Design Space Exploration

The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their designs at earlier design stages. In this paper we define the methodology we used to construct the STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-On-Chip) TLM simulation environment. This platform aims to provide a rapid and accurate design space exploration at higher levels of abstractions for multiprocessor system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. In order to assist the system designer to find the best MPSoC solution depending on the application, we used SystemC language for modeling and simulating the design. The platform includes models for OpenRISC ISSs, bus model based on wishbone protocol and memory models. The simulation is based on different high level of abstractions.

Combining Haar Wavelet and Karhunen Loeve Transforms for Medical Images Watermarking

This paper presents a novel watermarking method, applied to the medical imaging domain, used to embed the patients data into the corresponding image or set of images used for the diagnosis. The main objective behind the proposed technique is to perform the watermarking of the medical images in such a way that the three main attributes of the hidden information (i.e., imperceptibility, robustness, and integration rate) can be jointly ameliorated as much as possible. These attributes determine the effectiveness of the watermark, resistance to external attacks, and increase the integration rate. In order to improve the robustness, a combination of the characteristics of Discrete Wavelet and Karhunen Loeve Transforms is proposed. The Karhunen Loeve Transform is applied on the subblocks (sized 8 × 8) of the different wavelet coefficients (in the HL2, LH2, and HH2 subbands). In this manner, the watermark will be adapted according to the energy values of each of the Karhunen Loeve components, with the aim of ensuring a better watermark extraction under various types of attacks. For the correct identification of inserted data, the use of an Errors Correcting Code (ECC) mechanism is required for the check and, if possible, the correction of errors introduced into the inserted data. Concerning the enhancement of the imperceptibility factor, the main goal is to determine the optimal value of the visibility factor, which depends on several parameters of the DWT and the KLT transforms. As a first step, a Fuzzy Inference System (FIS) has been set up and then applied to determine an initial visibility factor value. Several features extracted from the Cooccurrence matrix are used as an input to the FIS and used to determine an initial visibility factor for each block; these values are subsequently reweighted in function of the eigenvalues extracted from each subblock. Regarding the integration rate, the previous works insert one bit per coefficient. In our proposal, the integration of the data to be hidden is 3 bits per coefficient so that we increase the integration rate by a factor of magnitude 3.

SVM approximation for real-time image segmentation by using an improved hyperrectangles-based method

A real-time implementation of an approximation of the support vector machine (SVM) decision rule is proposed. This method is based on an improvement of a supervised classification method using hyperrectangles, which is useful for real-time image segmentation. The final decision combines the accuracy of the SVM learning algorithm and the speed of a hyperrectangles-based method. We review the principles of the classification methods and we evaluate the hardware implementation cost of each method. We present the combination algorithm, which consists of rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present results obtained using Gaussian distribution and give an example of image segmentation from an industrial inspection problem. The results are evaluated regarding hardware cost as well as classification performances.

Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform

The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem, several methodologies can be used. These methodologies require automated methods to specify, generate and optimize the hardware, software, and the architectural interfaces between them. In this paper, we present a methodology flow for hardware-software communication synthesis for multiprocessor system-on-chip platform which are dedicated to streaming applications. Our methodology consists of high level architecture communication synthesis from functional description of the MPSoC design. The solution that we propose consists in synthesizing a custom bus architecture for the reconfigurable computing applications, which therefore allows minimizing hardware cost in the FPGA.

A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Abstract Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the best compromise between these approaches, we have developed the OORBIT tool (Offline/Online Relocation of Bitstreams) which accelerates the relocation time considerably. The methodology consists, firstly, in an offline bitstream modification phase which generates relocatable bitstreams including additional relocation data. Afterwards, online relocation is performed by a simple substitution of the initial location data by those calculated offline, corresponding to the target PRR. In this paper, we provide a detailed description of our methodology, emphasizing its interaction with the newest Xilinx Partition PR Design Flow, which results in major changes compared to previous efforts. Finally, a performance comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation more amenable.

Implementation of a real time image rotation using B-spline interpolation on FPGA's board

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGAs board. The method we used is based on M. Unsers work (1993) and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem, we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy on filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B-spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.The aim of our work is to realize the implementation of a real-time image rotation on FPGAs board. The method we used is based on a B-spline interpolator. The integration capicity of FPGAs is relatively weak, so the difficulty in this problem is to determine the right coding of the rotation filter while keeping a good accuracy on filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B-spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in order to determine the filter data coding.

Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA

This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder allows reducing significantly the number of logic cells (57%) in comparison with static implementation.