Elbert C. Hu

Adaptive fast path architecture

Adaptive Fast Path Architecture (AFPA) is a software architecture that dramatically improves the efficiency, and therefore the capacity, of Web and other network servers. The architecture includes a RAM-based cache that serves static content and a reverse proxy that can distribute requests for dynamic content to multiple servers. These two mechanisms are combined using a flexible layer-7 (content-based) routing facility. The architecture defines interfaces that allow these generic mechanisms to be exploited to accelerate a variety of application protocols, including HTTP. Efficiency is derived from maximizing the number of requests that are handled entirely within the kernel, using a deferred-interrupt context instead of threads wherever possible. AFPA has been implemented on several server platforms including Microsoft Windows NT® and Windows® 2000, OS/390®, AIX®, and most recently Linux. By conservative estimates, AFPA more than doubles capacity for serving static content compared to conventional server architectures, and has allowed IBM to establish a leadership position in Web server performance. A prototype implementation of AFPA on Linux delivers more than 10000 SPECweb96 operations per second on a single processor.

SIP server performance on multicore systems

This paper evaluates the performance of a popular open-source Session Initiation Protocol (SIP) server on three different multicore architectures. We examine the baseline performance and introduce three analysis-driven optimizations that involve increasing the number of slots in hash tables, an in-memory database for user authentication information, and incremental garbage collection for user location information. Wider hash tables reduce the search time and improve multicore scalability by reducing lock contention. The in-memory database reduces interprocess communication and locking. Incremental garbage collection smooths out peaks of both central processing unit and shared memory utilization, eliminating bursts of failed SIP interactions and reducing lock contention on the shared memory segment. Each optimization affects single-core performance and multicore scalability in different ways. The overall result is an improvement in absolute performance on eight cores by a factor of 16 and a doubling of multicore scalability. Results somewhat vary across architectures but follow similar trends, indicating the generality of these optimizations.

Trace driven modelling and performance evaluation of tightly coupled multiprocessor systems

The development and comparison of two trace-driven simulation models for microsystems with tightly coupled, shared-bus multiprocessors is presented. One model monitors the complete activities of processors, private caches, global bus, and main memory, while the other first abstracts local bus activities of processors, and then takes care of the multiprocessing interaction. The second model provides a means to move more quickly within the design space, while the first model can be used to select a final optimized design. Examples are presented to illustrate how these simulation models can help a complex choice among architectures, system configurations, and chip parameters for the design of an optimized microsystem.<<ETX>>