Elena Kakoulli

Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems

Hotspots are network-on-chip (NoC) routers or modules in multicore systems which occasionally receive packetized data from other networked element producers at a rate higher than they can consume it. This adverse phenomenon may greatly reduce the performance of NoCs, especially when wormhole flow-control is employed, as backpressure can cause the buffers of neighboring routers to quickly fill-up leading to a spatial spread in congestion. This can cause the network to saturate prematurely where in the worst scenario the NoC may be rendered unrecoverable. Thus, a hotspot prevention mechanism can be greatly beneficial, as it can potentially enable the interconnection system to adjust its behavior and prevent the rise of potential hotspots, subsequently sustaining NoC performance. The inherent unevenness of traffic patterns in an NoC-based general-purpose multicore system such as a chip multiprocessor, due to the diverse and unpredictable access patterns of applications, produces unexpected hotspots whose appearance cannot be known a priori, as application demands are not predetermined, making hotspot prediction and subsequently prevention difficult. In this paper, we present an artificial neural network-based (ANN) hotspot prediction mechanism that can be potentially used in tandem with a hotspot avoidance or congestion-control mechanism to handle unforeseen hotspot formations efficiently. The ANN uses online statistical data to dynamically monitor the interconnect fabric, and reactively predicts the location of an about to-be-formed hotspot(s), allowing enough time for the multicore system to react to these potential hotspots. Evaluation results indicate that a relatively lightweight ANN-based predictor can forecast hotspot formation(s) with an accuracy ranging from 65% to 92%.

HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips

The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots reduce the NoCs effective throughput, where in the worst case scenario, the entire network can be brought to an unrecoverable halt as a hotspot(s) spreads across the topology. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing functions, aiming to reduce the possibility of hotspots arising. Most, however, work passively, merely distributing traffic as evenly as possible among alternative network paths, and they cannot guarantee the absence of network congestion as their reactive capability in reducing hotspot formation(s) is limited. In this paper we present a new pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet routing across the network in an effort to mitigate any unforeseen near-future occurrences of hotspots. These ANNs are trained offline and during multicore operation they gather online buffer utilization data to predict about-to-be-formed hotspots, promptly informing the HPRA routing algorithm to take appropriate action in preventing hotspot formation(s). Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.

OctopusFS: A Distributed File System with Tiered Storage Management

The ever-growing data storage and I/O demands of modern large-scale data analytics are challenging the current distributed storage systems. A promising trend is to exploit the recent improvements in memory, storage media, and networks for sustaining high performance and low cost. While past work explores using memory or SSDs as local storage or combine local with network-attached storage in cluster computing, this work focuses on managing multiple storage tiers in a distributed setting. We present OctopusFS, a novel distributed file system that is aware of heterogeneous storage media (e.g., memory, SSDs, HDDs, NAS) with different capacities and performance characteristics. The system offers a variety of pluggable policies for automating data management across the storage tiers and cluster nodes. The policies employ multi-objective optimization techniques for making intelligent data management decisions based on the requirements of fault tolerance, data and load balancing, and throughput maximization. At the same time, the storage media are explicitly exposed to users and applications, allowing them to choose the distribution and placement of replicas in the cluster based on their own performance and fault tolerance requirements. Our extensive evaluation shows the immediate benefits of using OctopusFS with data-intensive processing systems, such as Hadoop and Spark, in terms of both increased performance and better cluster utilization.

An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs

Hotspots are network on-chip (NoC) routers or modules in systems on-chip (SoCs) which occasionally receive packetized traffic at a rate higher than they can consume it. This adverse phenomenon greatly reduces the performance of an NoC, especially in the case of today’s widely-employed wormhole flow-control, as backpressure can cause the buffers of neighboring routers to quickly fill-up leading to a spatial spread in congestion that can cause the network to saturate. Even worse, such situations may lead to deadlocks. Thus, a hotspot prevention mechanism can be greatly beneficial, as it can potentially enable the interconnection system to adjust its behavior and prevent the rise of potential hotspots, subsequently sustaining NoC performance and efficiency. Unfortunately, hotspots cannot be known a-priori in NoCs used in general-purpose systems as application demands are not predetermined unlike in application-specific SoCs, making hotspot prediction and subsequently prevention difficult. In this paper we present an artificial neural network-based hotspot prediction mechanism that can be potentially used in tandem with a hotspot avoidance mechanism for handling an unforeseen hotspot formation efficiently. The network uses buffer utilization statistical data to dynamically monitor the interconnect fabric, and reactively predicts the location of an about to-be-formed hotspot, allowing enough time for the system to react to these potential hotspots. The neural network is trained using synthetic traffic models, and evaluated using both synthetic and real application traces. Results indicate that a relatively small neural network can predict hotspot formation with accuracy ranges between 76% to 92% when evaluated on two different mesh NoCs.

A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores

Traffic hotspots, a severe form of network congestion, can be caused unexpectedly in a network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application traffic. Hotspots reduce the NoCs effective throughput, where in the worst-case scenario, network traffic flows can be frozen indefinitely. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing schemes, aiming to reduce the possibility of hotspots arising. Since most are not explicitly hotspotagnostic, they cannot completely prevent hotspot formation(s) as their reactive capability to hotspots is merely passive. This paper presents a pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network embedded artificial neural network-based (ANN) hotspot predictors to guide packet routing in mitigating any unforeseen near-future hotspot occurrences. First, these ANN-based predictors are trained offline and during multicore operation they gather online statistical data to predict about-to-be-formed hotspots, promptly informing HPRA to take appropriate hotspot-preventive action(s). Next, in a holistic approach, additional ANN training is performed with data acquired after HPRA interferes, so as to further improve hotspot prediction accuracy; hence, the ANN mechanism does not only predict hotspots, but is also aware of changes that HPRA imposes upon the interconnect infrastructure. Evaluation results, including utilizing real application traffic traces gathered from parallelized workload executions onto a chip multiprocessor architecture, show that HPRA can improve network throughput up to 81 percent when compared with prior-art. Hardware synthesis results affirm the HPRA mechanisms moderate overhead requisites.

Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics

On-chip electrical links exhibit large energy-to-bandwidth costs, whereas on-chip nanophotonics, which attain high throughput, yet energy-efficient communication, have emerged as an alternative interconnect in multicore chips. Here we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to existing die on-surface silicon nanophotonics. As nanophotonic components now reside subsurface, within the silica substrate, non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such Silicon-in-Silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a SiS-based mesh-interconnected topology with augmented diagonal optical channels that provides both higher effective throughput and throughput-to-power ratio versus prior-art.

Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics

With on-chip electrical interconnects being marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, form an alternative attractive counterpart. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrates subsurface non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial optical tools that such Silicon-In-Silica (SiS) structures are feasible, derive their geometry characteristics and design parameters, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links network-on-chip topology. In pushing the performance envelope even more, we next develop (1) an associated contention-aware photonic adaptive routing function, and (2) a parallelized photonic channel allocation scheme, that in tandem further reduce message delivery latency. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 30.8%, reduces communication latency by up to 22.5%, and improves the throughput-to-power ratio by up to 23.7% when compared to prior-art.

Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips

Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. In this paper we propose Hermes, a highly-robust, distributed fault-tolerant routing algorithm, whose performance degrades gracefully with increasing faulty NoC link counts. Hermes is a deadlock-free hybrid routing algorithm, utilizing load-balanced routing on fault-free paths, while providing pre-reconfigured escape routes in the vicinity of faults. An initial experimental evaluation shows that Hermes improves network throughput by up to 2.2× when compared against the existing state-of-the-art.

OctopusFS in action: tiered storage management for data intensive computing

The continuous improvements in memory, storage devices, and network technologies of commodity hardware introduce new challenges and opportunities in tiered storage management. Whereas past work is exploiting storage tiers in pairs or for specific applications, OctopusFS---a novel distributed file system that is aware of the underlying storage media---offers a comprehensive solution to managing multiple storage tiers in a distributed setting. OctopusFS contains auto-mated data-driven policies for managing the placement and retrieval of data across the nodes and storage tiers of the cluster. It also exposes the network locations and storage tiers of the data in order to allow higher-level systems to make locality-aware and tier-aware decisions. This demonstration will showcase the web interface of OctopusFS, which enables users to (i) view detailed utilization information for the various storage tiers and nodes, (ii) browse the directory namespace and perform file-related actions, and (iii) execute caching-related operations while observing their performance impact on MapReduce and Spark workloads.

Silica-Embedded Silicon Nanophotonic On-Chip Networks

On-chip nanophotonics offer high throughput, yet energy-efficient communication, traits that can prove critical to the continuance of multicore chip scalability. In this paper, we investigate and propose silicon nanophotonic components that are embedded entirely in the silica (SiO2) substrate, i.e., reside subsurface, as opposed to die on-surface silicon nanophotonics of prior-art. Among several offered advantages, such silicon-in-silica (SiS) nanophotonic structures empower the implementation of nonobstructive interconnect geometries that deliver an improved power-performance balance, as demonstrated experimentally. First, using exhaustive simulations based on commercial-grade optical software-based tools, we show that such SiS structures are feasible, and derive their geometry characteristics and design parameters. As a second step, utilizing SiS optical channels and filters, we then design two distinct SiS-based nanophotonic network-on-chip (PNoC) mesh-diagonal links topologies as a means of demonstrating our proof of concept. In further pushing the performance envelope, we next develop: 1) an associated contention-aware adaptive routing function and 2) a parallelized photonic channel allocation scheme, with both coupled to SiS-based PNoCs as elements, to respectively replace under-performing routing and flow-control photonic protocols currently utilized. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 59.7%, reduces communication latency by up to 78.7%, while improving the throughput-to-power ratio by up to 31.6% when compared to the state-of-the-art.