Elvi Räisänen-Ruotsalainen

A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-/spl mu/s input range has been integrated in a 1.2-/spl mu/m CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5/spl plusmn/0.5 V, and the operating temperature range is -40 to +60/spl deg/C. Single-shot accuracy is 3 ns and accuracy after averaging is /spl plusmn/120 ps with input time intervals 5-500 ns. In the total input range of 10 /spl mu/s, the final accuracy after averaging is /spl plusmn/200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm/spl times/2.5 mm. >

An integrated time-to-digital converter with 30-ps single-shot precision

A time-to-digital converter (TDC) with 32-ps resolution and 2.5-/spl mu/s measurement range has been integrated in a 0.8-/spl mu/m BiCMOS process. The TDC is based on a counter with a 100-MHz clock. Two separate time digitizers improve the time resolution by interpolating within the clock period. These interpolators are based on analog dual-slope conversion. According to test results, the single-shot precision of the TDC is better than 30 ps (/spl sigma/-value) and the nonlinearity is less than /spl plusmn/5 ps when input time intervals range from 10 ns to 2.5 /spl mu/s. The conversion time is /spl les/6.3 /spl mu/s. Temperature drift, excluding the temperature dependence of the oscillator, is below /spl plusmn/40 ps in the temperature range of -40 to 60/spl deg/C. The size of this chip, including pads, is 3.5/spl times/3.4 mm/sup 2/ and its power consumption is 350 mW.

Design of a 1 V low power CMOS bandgap reference based on resistive subdivision

The design of a CMOS bandgap reference (BGR), for portable applications with medium accuracy, is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 0.750 V with 1/spl sigma/ variation of 10 mV (1.3%) without trimming with a supply voltage range from 1 V to 1.6 V and temperature range of -20/spl deg/C-50/spl deg/C measured from 10 samples. The maximum supply current is 4.5 /spl mu/A and the area of the design is /spl sim/0.13 mm/sup 2/ with a standard 0.35 /spl mu/m double-poly n-well CMOS process.

A 1-V 5 /spl mu/W CMOS-opamp with bulk-driven input transistors

In this paper, a low-power CMOS operational amplifier for biomedical instrumentation operating with a 1-V supply is described. Large input common-mode range (CMR) is achieved utilizing bulk-driven PMOS-transistors as an input differential pair of the opamp. The opamp was fabricated in a 0.35 /spl mu/m n-well double-poly CMOS process with threshold voltages of 0.5 V and 0.65 V. The open-loop gain (A/sub 0/) of the amplifier is 70 dB, the gain-bandwidth product (GBW) is 190 kHz and the phase margin (PM) is 60/spl deg/ with a 7 pF load. The power consumption of the opamp is 5 /spl mu/W.

Time interval measurements using time-to-voltage conversion with built-in dual-slope A/D conversion

An integrated CMOS circuit for measuring a time interval given as the width of a pulse is presented. The circuit converts the time interval to be measured to a longer interval which can be digitized more accurately using a clock than the initial one. The circuit is a combination of a time-to-voltage converter (TVC) and a dual-slope A/D converter. In the time-to-voltage conversion a capacitor is discharged with a constant current during the time interval to be measured. The use of dual-slope A/D conversion reduces the effects of current and capacitance value drifting due to temperature changes. The measurement range (50-500 ns) can be scaled with the discharging current (12-90 mu A). The resolution of the time-to-voltage conversion is 200 ps or better. The A/D conversion uses a 10 MHz clock for digitization, giving an overall resolution of 400 ps.<<ETX>>

A time digitizer with interpolation based on time-to-voltage conversion

A time-to-digital converter (TDC) based on a main counter and two analog interpolators has been implemented. The clock frequency of the TDC is 100 MHz and the interpolators have been implemented with a time-to-voltage converter followed by a 10-bit A/D converter. According to test results, the single-shot resolution of the TDC is 30 ps (/spl sigma/-value) and nonlinearity is less than /spl plusmn/10 ps when input time intervals range from 10 ns to 2.5 /spl mu/s. Uncompensated temperature drift in the temperature range -35/spl deg/C to +60/spl deg/C was measured to be 150 ps including the temperature dependency of the reference clock.

A 1-V, self adjusting, 5-MHz CMOS RC-oscillator

A 5-MHz, self adjusting CMOS RC-oscillator for portable biomedical applications is presented. The oscillator is capable of operating. with a 1-V power supply and it features low current consumption (20 /spl mu/A @ 1 V) and low sensitivity to supply voltage and temperature variations. The total accuracy of the oscillator is within 5 % with component tolerances of 1 % in external elements R and C. The design was fabricated in a 0.35 /spl mu/m n-well standard digital CMOS process with threshold voltages of 0.5 V and -0.65 V. The design and the operation of the RC-oscillator with measurement results of fabricated chips are presented.

A 1.2 V micropower CMOS op amp with floating-gate input transistors

A micropower 1.2 V op amp has been integrated in a 0.35 /spl mu/m CMOS process. Floating-gate input transistors are used to increase the input common mode voltage range of the op amp. Measured dc gain of the op amp is 65 dB. With a 9 pF load unity gain bandwidth is 230 kHz and phase margin is 62/spl deg/. Input referred noise is 0.5 /spl mu/V//spl radic/(Hz) at 10 Hz and 0.15 /spl mu/V/(Hz) at 10 kHz. Current consumption of the op amp is 4.3 /spl mu/A and active area is 0.11 mm/sup 2/.

A low-power 5.4 kHz CMOS gm-C bandpass filter with on-chip center frequency tuning

A 5.4 kHz, 6th-order elliptic bandpass gm-C filter for portable biomedical applications is described. The circuit includes automatic on-chip center frequency tuning utilizing a 32 kHz system clock as a reference. The aim was to minimize filter area and power consumption. The design has been integrated in a 0.6 /spl mu/m CMOS process. Core area is 1.07 mm/sup 2/ of which the tuning circuitry constitutes 0.24 mm/sup 2/. Measured current consumption of the filter including tuning circuitry is 18 /spl mu/A with a 3 V supply voltage.

A BiCMOS time-to-digital converter with 30 ps resolution

A time-to-digital converter (TDC) with 32 ps LSB and 2.5 /spl mu/s measurement range has been implemented in a 0.8 /spl mu/m BiCMOS process. The TDC is based on a main counter and two separate time digitizers for interpolation inside the clock period. The clock frequency of the counter is 100 MHz and the interpolators are based on dual-slope conversion. According to test results, the single-shot resolution of the TDC is 30 ps (/spl sigma/-value) and nonlinearity is less than /spl plusmn/5 ps when input time intervals range from 5 ns to 2.5 /spl mu/s. The conversion time is <6.3 /spl mu/s. Temperature drift, excluding the temperature dependence of the oscillator, is below /spl plusmn/40 ps in a temperature range of -40-+60/spl deg/C. The size of this chip, including pads, is 3.4 mm/spl times/3.4 mm and its power consumption is 350 mW.