Eman A. Soliman

New CMOS fully differential current conveyor and its application in realizing sixth order complex filter

A sixth order complex filter based on the usage of a newly proposed fully differential current conveyor (FDCC) is presented in this paper. The FDCC new structure is based on usage of differential difference operational floating amplifier (DDOFA) [1] and floating current source circuits [2]. The block is realized using 0.25µm CMOS technology under ±1.5V power supply. PSPICE simulation for the FDCC is done for testing the block. The simulation shows that the FDCC has ±0.5V input dynamic range, 95MHz 3-dB frequency at output terminal under 10KΩ load and 7.21mW total power dissipation. The FDCC is used to realize first order complex filter with 1 MHz center frequency and second order complex filter at 500 KHz center frequency. Finally; using cascading technique, a sixth order complex filter at 500 KHz center frequency is proposed. The proposed filter is suitable for applications like Bluetooth receivers. All the proposed filter circuits are simulated using ADS simulator.

LOW VOLTAGE CURRENT CONVEYOR-BASED FIELD PROGRAMMABLE ANALOG ARRAY

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1 V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of ±0.5 V.

MULTI-STANDARD RECEIVER BASEBAND CHAIN USING DIGITALLY PROGRAMMABLE OTA BASED ON CCII AND CURRENT DIVISION NETWORKS

In this paper, a digitally programmable OTA based multi-standard receiver baseband chain is presented. The multistandard baseband receiver section consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF filter. The receiver is suitable for Bluetooth/UMTS/WLAN/WiMAX standards. Three different programmable OTA architectures based on second generation current conveyors (CCII) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and has good linearity - better than -50dB HD3- is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6mW. The DC gain varies over a 68dB range with 1MHz to 13.6MHz programmable bandwidth. The receiver baseband chain is realized using 90nm CMOS technology model under ±0.5V voltage supply.

Digitally programmable second generation current conveyor-based FPAA

A novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The programmability of the proposed DPCCII is achieved using three-bit MOS R-2R ladder current division network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is 72.3 mW from 1 V voltage supply. A second-order programmable universal filter is realized using the proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS technology model under balanced supply voltage of ±0.5 V. Copyright

High speed fully differential second generation current conveyor

In this paper, a high speed fully differential second generation current conveyor (FDCCII+) is presented. The proposed FDCCII+ is based on using fully differential buffer [1] and class AB push-pull output stage with a new standby current control circuitry. The circuit is realized using 90nm CMOS TSMC technology model under 1.2V single supply voltage. The proposed realization of FDCCII+ input differential voltage dynamic range is from −0.45V to 0.45V. The total power dissipation of the circuit is 1.7mW. The simulated bandwidth of the FDCCII+ is 254MHz under 10KΩ load at X and Z terminals. All the circuit simulations are done using Cadence Virtuoso SPECTRE circuit simulator.

Voltage-mode Field Programmable Analog Array using Second Generation Current Conveyor

A voltage mode Field Programmable Analog Array (FPAA) is presented in this paper. The FPAA is an array consisting of 30 Digitally Programmable Second Generation Current Conveyors (DPCCII-). The FPAA is made from seven configurable analog blocks (CABs) formed with DPCCII-. The CABs are directly connected to each other through direct wiring. This direct wiring methodology is realized because the DPCCII- outputs can be set to zero using a three-bit digital codeword. The FPAA is realized using 90nm CMOS technology model. The standby DC power consumption of the FPAA is 72.3mW from balanced supply voltage °0.5V. A tunable second order universal filter is realized using the proposed FPAA. The filters cutoff frequency is tuned from 5.8MHz to 11.6MHz.

Reconfigurable baseband chain for Software-Defined Radio receivers

This paper presents single amplifier biquads and Active-gm-RC cells with programmable unity gain frequency operational amplifiers. A complete baseband chain for Software-Defined Radio is designed using these building blocks. The baseband chain consists of a reconfigurable low pass filter (LPF) and a variable gain amplifier (VGA). The LPF is a sixth order filter with cutoff frequency range from 380 kHz to 33.4 MHz. The VGA is made of two cascaded gain stages. The baseband chain is realized in 0.25µm CMOS technology with 1.2V supply voltage. PSPICE simulations are presented.

THE DIFFERENTIAL DIFFERENCE OPERATIONAL FLOATING AMPLIFIER: NEW CMOS REALIZATIONS AND APPLICATIONS

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.

Sixth order baseband variable LPF using new tunable operational amplifier

A sixth order reconfigurable low pass filter (LPF) is realized in this paper using 0.25µm CMOS technology model. The filter is based on cascading connection of bi-quadratic Active-Gm-RC cells. The Active-Gm cells are realized using compensated op-amps with variable transconductance gain and variable compensation capacitors (Variable Gm-Cc op-amp). The tuning range of the filters cutoff frequency is from 77.4 KHz to 37.78MHz. The filter operates from single supply of 1.7V. Simulations results using PSPICE for the proposed reconfigurable LPF are presented. Comparisons with previous work in [1] are included to view the points of strength for the proposed architecture.

High bandwidth Second Generation Current Conveyor based Operational Transconductance Amplifier

A high bandwidth CMOS fully differential tunable Second Generation Current Conveyor (CCII) based Operational Transconductance Amplifier (OTA) is introduced. The fully differential OTA is realized using two single-ended CCIIs. The OTA is tuned via a variable MOS resistor. The transconductance gain (Gm) is varied from 300.64µA/V to 1011.07µA/V. The tunable OTA is used to realize a third order Gm-C low pass filter with tunable cut-off frequency. The tuning range of the filters cut-off frequency varies from 48.42MHz to 130.32MHz. LTSPICE simulation results for both the OTA and the filter using the 90nm CMOS technology model with 1V single-ended voltage supply are presented.