Emeric Brun

Competing Energy Lookup Algorithms in Monte Carlo Neutron Transport Calculations and Their Optimization on CPU and Intel MIC Architectures

Abstract The Monte Carlo method is a common and accurate way to model neutron transport with minimal approximations. However, such method is rather time-consuming due to its slow convergence rate. More specifically, the energy lookup process for cross sections can take up to 80% of overall computing time and therefore becomes an important performance hotspot. Several optimization solutions have been already proposed: unionized grid, hashing and fractional cascading methods. In this paper we revisit those algorithms for both CPU and manycore (Intel MIC) architectures and introduce vectorized versions. Tests are performed with the PATMOS Monte Carlo prototype, and algorithms are evaluated and compared in terms of time performance and memory usage. Results show that significant speedup can be achieved over the conventional binary search on both CPU and Intel MIC. Further optimization with vectorization instructions has been proved very efficient on Intel MIC architecture due to its 512-bit Vector Processing Unit (VPU); on CPU this improvement is limited by the smaller VPU width.

Competing energy lookup algorithms in Monte Carlo neutron transport calculations and their optimization on CPU and Intel MIC architectures

Abstract The Monte Carlo method is a common and accurate way to model neutron transport with minimal approximations. However, such method is rather time-consuming due to its slow convergence rate. More specifically, the energy lookup process for cross sections can take up to 80% of overall computing time and therefore becomes an important performance hot-spot. Several optimization solutions have been already proposed: unionized grid, hashing and fractional cascading methods. In this paper we revisit those algorithms for both CPU and Many Integrated Core (MIC) architectures and introduce vectorized versions. Tests are performed with the PATMOS Monte Carlo prototype, and algorithms are evaluated and compared in terms of time performance and memory usage. Results show that significant speedup can be achieved over the conventional binary search on both CPU and MIC. Using vectorization instructions has been proved efficient on manycore architecture due to its 512-bit Vector Processing Unit (VPU); on CPU this improvement is limited by the smaller VPU width. Further optimization like memory reduction turns out to be very important since it largely improves computing performance.

Efficient Cross Section Reconstruction on Modern Multi and Many Core Architectures.

The classical Monte Carlo (MC) neutron transport employs energy lookup on long tables to compute the cross sections needed for the simulation. This process has been identified as an important performance hotspot of MC simulations, because poor cache utilization caused by random access patterns and large memory footprint makes it unfriendly to modern architectures. A former study [1] shows that such method presents little vectorization potential in a real-case simulation due to the memory-bound nature. In this paper, we revisit a cross section reconstruction method introduced by Hwang [2] to evaluate another solution. The reconstruction converts the problem from memory-bound to compute-bound. Only several variables for each resonance are required instead of the conventional pointwise table covering the entire resolved resonance region. Though the memory space is largely reduced, this method is really time-consuming. After a series of optimizations, results show that the reconstruction kernel benefits well from vectorization and can achieve 1806 GFLOPS (single precision) on a Knights Landing 7250, which represents 67% of its effective peak performance.

Pre-exascale Architectures: OpenPOWER Performance and Usability Assessment for French Scientific Community

Exascale implies a major pre-requisite in terms of energy efficiency, as an improvement of an order of magnitude must be reached in order to stay within an acceptable envelope of 20 MW. To address this objective and to continue to sustain performance, HPC architectures have to become denser, embedding many-core processors (to several hundreds of computing cores) and/or become heterogeneous, that is, using graphic processors or FPGAs. These energy-saving constraints will also affect the underlying hardware architectures (e.g., memory and storage hierarchies, networks) as well as system software (runtime, resource managers, file systems, etc.) and programming models. While some of these architectures, such as hybrid machines, have existed for a number of years and occupy noticeable ranks in the TOP 500 list, they are still limited to a small number of scientific domains and, moreover, require significant porting effort. However, recent developments of new paradigms (especially around OpenMP and OpenACC) make these architectures much more accessible to programmers. In order to make the most of these breakthrough upcoming technologies, GENCI and its partners have set up a technology watch group and lead collaborations with vendors, relying on HPC experts and early adopted HPC solutions. The two main objectives are providing guidance and prepare the scientific communities to challenges of exascale architectures.