Emil Slusanschi

Mapping data mining algorithms on a GPU architecture: a study

Data mining algorithms are designed to extract information from a huge amount of data in an automatic way. The datasets that can be analysed with these techniques are gathered from a variety of domains, from business related fields to HPC and supercomputers. The datasets continue to increase at an exponential rate, so research has been focusing on parallelizing different data mining techniques. Recently, GPU hybrid architectures are starting to be used for this task. However the data transfer rate between CPU and GPU is a bottleneck for the applications dealing with large data entries exhibiting numerous dependencies. In this paper we analyse how efficient data mining algorithms can be mapped on these architectures by extracting the common characteristics of these methods and by looking at the communication patterns between the main memory and the GPUs shared memory. We propose an experimental study for the performance of memory systems on GPU architectures when dealing with data mining algorithms and we also advance performance model guidelines based on the observations.

A reward-based routing protocol to reduce the EMF exposure over wireless mesh networks

This paper presents Reward Based Routing Protocol (RBRP), a novel routing protocol for wireless mesh networks, that aims at reducing and fairly distributing the Electromagnetic Field (EMF) Exposure caused by wireless transmissions. The basis of this protocol is a reward-based scheme in which intermediate nodes forward packets and receive a reward proportional to the degree of exposure they generate. By means of a simulation campaign over the NS-3 framework, we assess that RBRP clearly outperforms a legacy approach in terms of exposure, while it does not show a worse behaviour, when considering other figures of merit.

Image vectorization on modern architectures

This work presents an image vectorization application aimed to exploit features found in most of todays modern architectures. Design decisions supported by performance results are presented along with use cases for the proposed solution. We will present the algorithm, the target architectures and threading models, as well as a number of optimization techniques. Finally results of both low power SoC and high performance multicore processors are discussed.

Towards efficient video compression using scalable vector graphics on the Cell/B.E.

With the emergence of multi-core CPUs, parallel computing has made the leap from being a paradigm mainly used in high performance computing to imposing itself as one of the standards used in mainstream computing. The field of video compression and decompression naturally embraces parallel computing since video compression is a computationally intensive task that can be successfully distributed among two or more computing cores. This paper describes a different approach to video compression based on image vectorization on the novel Cell/B.E. architecture. Video frames are analyzed and interesting features such as edges, corners and patches are extracted, with significant performance speedups obtained on the Cell processor and maintaining good image quality. Finally, the features and the topological relations between them are used to reconstruct the original image.

ADiJaC -- Automatic Differentiation of Java Classfiles

This work presents the current design and implementation of ADiJaC, an automatic differentiation tool for Java classfiles. ADiJaC uses source transformation to generate derivative codes in both the forward and the reverse modes of automatic differentiation. We describe the overall architecture of the tool and present various details and examples for each of the two modes of differentiation. We emphasize the enhancements that have been made over previous versions of ADiJaC and illustrate their influence on the generality of the tool and on the performance of the generated derivative codes. The ADiJaC tool has been used to generate derivatives for a variety of problems, including real-world applications. We evaluate the performance of such codes and compare it to derivatives generated by Tapenade, a well-established automatic differentiation tool for Fortran and C/C++. Additionally, we present a more detailed performance analysis of a real-world application. Apart from being the only general-purpose automatic differentiation tool for Java bytecode, we argue that ADiJaC’s features and performance are comparable to those of similar mature tools for other programming languages such as C/C++ or Fortran.

Routing algorithm to fairly distribute the exposure to electromagnetic fields over wireless mesh networks

This work presents a novel model for multi-hop networks which aims to include electro-magnetic exposure metrics within the routing paradigm. Given the need to include new metrics in the routing decision making, as a prelude to the protocols definition, it is deemed necessary the definition of novel network models and adequate algorithms so that they can be afterwards utilized to assess the performance of the routing protocols. In particular, this work proposes a network model to include the electro-magnetic exposure within the routing costs; besides, an algorithm (Cycle Canceling Algorithm) has been identified that is able to effectively solve the problem resulting from the model. Furthermore, the behavior of the proposed algorithm is compared with other which considers a different metric, so as to corroborate its operation and to provide information on how to tweak its configuration parameters.

Challenges and Current Results of the TWISNet FP7 Project

Over the past years, the deployment of sensor networks in industrial environments has attracted much attention in several business domains. An increasing number of applications have been developed, ranging from defense, public security, energy management, traffic control to health care. Sensor networks are particularly interesting due to their ability to control and monitor physical environments. Nevertheless, several technical (e.g. remote management, deployment) and security (e.g. user’s privacy, data confidentiality and reliability) challenges deter their integration in industrial processes. This extended abstract presents an overview of the current research results on an architecture aiming at supporting and securing the integration of sensor networks into large scale industrial environments. This work is carried out in the “TWISNet: Trustworthy Wireless Industrial Sensor Networks” project financially supported by the EC under grant agreement FP7-ICT-258280.

Framework for Mapping Data Mining Applications on GPUs

Data mining algorithms are expensive by nature, but when dealing with todays dataset sizes, they are becoming even more slow and hard to use. Previous work has focused on parallelizing data mining algorithms on different architectures, and more recently, applications are starting to take advantage of the massive computation power and high bandwidth offered by GPUs. However there has been almost no prior work in offering a general methodology for parallelizing all types of data mining applications on hybrid architectures. This paper presents a framework for fast and efficient parallelization of data mining algorithms on GPU systems. The framework implements I/O transfer models that deal with the huge amount of data entries which are processed by this type of algorithms, all with numerous dependencies. Also the framework allows users to specify data requirements for each task so that the data scheduler can map efficiently each task on a GPU node and on a block in each of these processors improving the overall performance of the algorithm with around 20%.

Cell GAF - a genetic algorithms framework for the cell Broadband Engine

This paper proposes Cell GAF, a complete framework for developing genetic algorithms, optimized for the Cell Broadband Engine architecture. Testing the qualities of the implementation on the Knapsack problem have shown that the use of the Cell/B.E. processor brings significant increases in performance of a factor of 5 to 9 times compared to classical quad core x86 processors. Similarly, the various operators in the Cell/B.E. implementations of the genetic algorithms were found to be on average 5 times faster than their x86 counterparts.