Emran Mohd Tamil

High-Speed Shortest Path Co-processor Design

Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior.

An efficient network security system through an ontology approach

Ontology analysis has been shown to be an effective first step in the construction of robust knowledge based system. Moreover, the popularity of semantic technologies and the semantic Web has provided several beneficial opportunities for the modeling and computer security communities of interest. This paper describes the role of ontologies in facilitating network security modeling. It outlines the technical challenges in distributed network security simulation modeling and describes how ontology-based methods may be applied to address these challenges. The paper concludes by describing an ontology-based solution framework for network security simulation modeling and analysis and outlining the benefits of this solution approach.

A Review on Feature Extraction & Classification Techniques for Biosignal Processing (Part V: Gait Signal)

This paper concentrates on Gait signal processing with the emphasis on Parkinsons’s Disease diagnosis. Gait is a novel biometric intended to recognize human from their walking pattern. This paper discussed in general about feature extraction and classification for Gait application. Among the factor discussed and analysed include the techniques advantages, performance and drawbacks.

Feature Extraction for Biosignal Processing (Part IV: Electrogastrogram) using HHT

This paper concentrates on Electrogastrogram (EGG). This paper reviews previous feature extraction and classification technique used in electrogastrogram signal analysis. This paper discussed more into more depth on Hilbert Huang Transform for feature extraction. Among the factor discussed and analyzed include the techniques advantages, performance and drawbacks.

Intersection and Complement Set (IACS) Method to Reduce Redundant Node in Mobile WSN Localization

The majority of the Wireless Sensor Network (WSN) localization methods utilize a large number of nodes to achieve high localization accuracy. However, there are many unnecessary data redundancies that contributes to high computation, communication, and energy cost between these nodes. Therefore, we propose the Intersection and Complement Set (IACS) method to reduce these redundant data by selecting the most significant neighbor nodes for the localization process. Through duplication cleaning and average filtering steps, the proposed IACS selects the normal nodes with unique intersection and complement sets in the first and second hop neighbors to localize the unknown node. If the intersection or complement sets of the normal nodes are duplicated, IACS only selects the node with the shortest distance to the blind node and nodes that have total elements larger than the average of the intersection or complement sets. The proposed IACS is tested in various simulation settings and compared with MSL* and LCC. The performance of all methods is investigated using the default settings and a different number of degree of irregularity, normal node density, maximum velocity of sensor node and number of samples. From the simulation, IACS successfully reduced 25% of computation cost, 25% of communication cost and 6% of energy consumption compared to MSL*, while 15% of computation cost, 13% of communication cost and 3% of energy consumption compared to LCC.The majority of the Wireless Sensor Network (WSN) localization methods utilize a large number of nodes to achieve high localization accuracy. However, there are many unnecessary data redundancies that contributes to high computation, communication, and energy cost between these nodes. Therefore, we propose the Intersection and Complement Set (IACS) method to reduce these redundant data by selecting the most significant neighbor nodes for the localization process. Through duplication cleaning and average filtering steps, the proposed IACS selects the normal nodes with unique intersection and complement sets in the first and second hop neighbors to localize the unknown node. If the intersection or complement sets of the normal nodes are duplicated, IACS only selects the node with the shortest distance to the blind node and nodes that have total elements larger than the average of the intersection or complement sets. The proposed IACS is tested in various simulation settings and compared with MSL* and LCC. The performance of all methods is investigated using the default settings and a different number of degree of irregularity, normal node density, maximum velocity of sensor node and number of samples. From the simulation, IACS successfully reduced 25% of computation cost, 25% of communication cost and 6% of energy consumption compared to MSL*, while 15% of computation cost, 13% of communication cost and 3% of energy consumption compared to LCC.

Parallel Matrix Multiplication Design for Monocular SLAM

As software profiling is conducted to determine which section of program demand high processing computation in monocular SLAM inverse depth estimation, matrix multiplication is identified to be one of the most time consuming process. The processing is more demanding when the number of features inserted to the image is increased. For that reason, this paper proposes a parallel matrix multiplier design which could accelerate the execution time. In this design, Field Programmable Gate Array (FPGA) technology which allows parallel design to be implemented is presented. The design manipulates existing classical matrix multiplication algorithm into an architecture that would enable data to be processed concurrently.