En Yunfei

The relationship between LED package and reliability

Package is a key factor, and affects the reliability of LED. In this paper, the main failure modes and mechanisms that caused by poor package process were investigated through some failure analysis cases, and some improving methods to improve the LEDs reliability are put forward.

Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide

Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/Vs to 363.65 cm2/Vs. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10−10 V2Hz−1 and 2.7×10−8 V2Hz−1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm−3eV−1 to 6.16×1018 cm−3eV−1. Based on carrier mobility fluctuation theory, the extracted average Hooges parameter in these devices increases from 3.92×10−5 to 1.34×10−2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 Mrad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are −10.82 V and −31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.

Critical factors on the hermetic characteristics of DC/DC power module

The hermeticity of DC/DC power module was analyzed by using finite element thermal analysis software ANSYS to address the critical factors on the reliability issues of glass insulator (or hermeticity). It was found that shell structure parameters, such as the diameter and shape of hole, the thickness of cover and bottom board, especially the boundary constraints make significant influences on the hermitcity of DC/DC during assembly and testing.

The effect of Pb contamination on the solidification behaviors and mechanical properties of backward compatible solder joints

The Pb contamination on the solidification behaviors and shear properties of Backward Compatible solder joints were investigated. The solidification behavior of solder and joint examined by using a DSC instrument, and it was found that the addition of Pb in Sn3.0Ag0.5Cu would change the primary phase during solidification and change the microstructure of backward compatible solder and joint, meantime, it is easy form a low melting temperature Sn-Ag-Pb ternary eutectic alloy, and the pasty rang between two endothermic(or exothermic) peak decreases with the increasing of Pb content in solder matrix. The discrepancy in solidification behavior results in different microstructures significantly. The average sizes of β-Sn and IMC particles(Ag3Sn and Cu6Sn5) in solder matrix are larger than those in Sn3.0Ag0.5Cu solder relatively. However, the shear force of backward compatible mixed joints is higher than SAC/Cu joint independent of Pb content when Pb content in solder matrix is less than 30 wt.% by using ball shear test, it seems that the low melting temperature Sn-Ag-Pb has little influence on the shear properties of mixed joints with a single interface in as-solidified condition. The addition of Pb in Sn3.0Ag0.5Cu solder apparently facilitated the slip of β-Sn and stress release under shear stress to some extent.

Optimal design of package structure of the hybrid integrated DC/DC power module based on orthogonal experimental method

The hybrid integrated DC/DC power modules are being used in many field, however, the operating temperature of the components becomes higher with the increasing density of the power module assembly. In this paper, orthogonal experimental design method is used to study the variation trend of DC/DC power module package thermal performance with combination of different package structure material and parameters, thus determining primary and secondary order of factor which has an influence on package heat dissipation and obtaining optimum combination of package structure parameters. The results of finite element simulation analysis shows that adopting the optimum combination of package structure parameters can decrease the chips junction temperature.

Low-frequency noise characteristics in the MOSFETs processed in 65 nm technology*

Low-frequency noise behavior in the MOSFETs processed in 65 nm technology is investigated in this paper. Low-frequency noise for NMOS transistors agrees with McWhorters theory (carrier number fluctuation), low-frequency noise in the sub-threshold regime agrees with McWhorters theory for PMOS transistors while it agree with Hooges theory (carrier mobility fluctuation) in the channel strong inversion regime. According to carrier number fluctuation model, the extracted trap densities near the interface between channel and gate oxide for NMOS and PMOS transistor are 3.94 × 1017 and 3.56 × 1018 cm−3/eV respectively. According to carrier mobility fluctuation model, the extracted average Hooges parameters are 2.42 × 10−5 and 4 × 10−4. By consideration of BSIM compact model, it is shown that two noise parameters (NOIA and NOIB) can model the intrinsic channel noise. The extracted NOIA and NOIB are constants for PMOS and their values are equal to 3.94 × 1017 cm−3/eV and 9.31 × 10−4 V−1. But for NMOS, NOIA is also a constant while NOIB is inversely proportional to the effective gate voltage. The extracted NOIA and NOIB for NMOS are equal to 3.56 × 1018 cm−3/eV and 1.53 × 10−2 V−1. Good agreement between simulation and experimental results is achieved.

Harmonic vibration analysis and S-N curve estimate of PBGA mixed solder joints

With the development of lead-free in electronic products, mixed soldering of lead-free component with lead solder is inevitable in high reliability electronic assembly. For the mixed assemblies, the primary task is to ensure the reliability of mixed solder joints. This study is aimed at finding out the harmonic vibration fatigue properties of plastic ball grid array (PBGA) mixed solder joints under 1st natural frequency and getting the relation curve between equivalent stress and number of fatigue cycles of the mixed solder joints. A specified PBGA assembly was designed with a piece of daisy-chained printed circuit board (PCB). Modal test and harmonic vibration test were implemented. The PCB strain was measured by strain gages, and the time to failure of solder joints was monitored by an event detector. After comparing natural frequencies, modal shapes and PCB strain with the simulation corresponding results, finite element model (FEM) was validated. Then, the volume averaged equivalent stress of mixed solder joints was discovered with modified model. Finally, S-N curve of mixed solder joints was fitted with Basquin power law relation. In the hopeful future, combining the fitted S-N curve with other methodologies, the vibration fatigue life of mixed solder joints could be estimated.

The coupling effect of size effect and Krikendall voids on the fracture features of Ni/Sn3.0Ag0.5Cu/Cu joint

In this study, the formation mechanisms of Kirkendall voids in Sn3Ag0.5Cu/Cu and Ni/Sn3Ag0.5Cu/Cu joints were investigation, and the coupling effect of joint size and Kirkendall voids on the fracture features of Ni/SnAgCu/Cu joints were also studied. It was found that the size effect had a significant influence on the formation of Kirkendall voids at Cu side in Sn3Ag0.5Cu/Cu and Ni/Sn3Ag0.5Cu/Cu joint, the ratio of Kirkendall voids to the total area of Cu3Sn layer increased with solder volume irrespective of the structure of joint. The coupling effect of Ni and Cu inhibited the growth of Cu3Sn significantly and increased the ratio of Kirkendall voids to the total area of Cu3Sn layer. However, the Kirkendall effect seems to have no obvious influence on the fracture features of Ni/ Sn3Ag0.5Cu /Cu joints compared with Cu/Sn3Ag0.5Cu/Cu joint by using lap-shear test method.

The HCI effect reliability evaluation of CMOS process

Hot Carrier Injection (HCI) effect in the device of CMOS process has been studied, and the mechanism of HCI effect has been analyzed. In the Accelerated stress conditions, the accelerated life test of HCI effect has been conducted, and the reliability of 0.35μm~0.13μm CMOS process has been evaluated by the calculation of lifetime. The results show that the lifetime of HCI effect is not the same in different process node. The lifetimes of HCI effect in three different aspect ratio devices fabricated in 0.13μm CMOS process indicate that there is no relation between the aspect ratio of device and the lifetime of HCI effect.

Research on tin whisker growth of pure tin plating of different lead substrates

To study the tin whisker growth behavior of different lead substrates, five kinds of lead frames were designed as plating substrates and the pure tin were electroplated onto the substrates respectively, then the thermal shock, high temperature/humidity storage, and the ambient temperature/humidity storage test were performed under the annealing and un-annealing conditions, and the effect of lead substrates on the crystal structures of Sn plating was analyzed and the influence of environment condition, crystal structure, annealing process on the tin whisker growth was studied. The results showed that the Sn plating of brass frame was easier to grow tin whisker than other lead frames because of bigger crystal sizes and smaller boundary interspaces of grains, The temperature change condition was the best external driving force, The capability of anti-tin whisker was excellent for Sn plating of C7025 substrate plating, and the external environment had a great impact to the tin whisker growth of 42 alloy substrate plating. At last, the annealing process was available to slow down the growth of tin whisker under isothermal condition.