Enver Cavus

A performance improvement and error floor avoidance technique for belief propagation decoding of LDPC codes

In this work, we introduce a unique technique that improves the performance of the BP decoding in waterfall and error-floor regions by reversing the decoder failures. Based on the short cycles existing in the bipartite graph, an importance sampling simulation technique is used to identify the bit and check node combinations that are the dominant sources of error events, called trapping sets. Then, the identified trapping sets are used in the decoding process to avoid the pre-known failures and to converge to the transmitted codeword. With a minimal additional decoding complexity, the proposed technique is able to provide performance improvements for short-length LDPC codes and push or avoid error-floor behaviors of longer codes

An IS Simulation Technique for Very Low BER Performance Evaluation of LDPC Codes

We introduce an Importance Sampling (IS) method that successfully simulates the performance of Low density Parity Check (LDPC) Codes in an AWGN channel at very low bit error rates (BERs). By effectively finding and biasing bit node combinations that are the dominant sources of error events, called trapping sets, the developed technique provokes more frequent decoder failures. Consequently, fewer simulation runs and higher simulation gains are achieved. Regardless of the block size of an LDPC code, only a few dominant trapping set classes cause decoder failures at low BER regions. Therefore, the proposed technique allows the performance evaluation for any size LDPC code at very low BER regions with remarkable simulation gains. For BERs of 10-20, we observed simulation gains on the order of 1014.

Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets

We introduce an importance sampling (IS) method that successfully simulates the performance of Low density Parity Check (LDPC) Codes in an AWGN channel at very low bit error rates (BERs). By effectively finding and biasing bit node combinations that are the dominant sources of error events, called trapping sets, the developed technique provokes more frequent decoder failures. Consequently, fewer simulation runs and higher simulation gains are achieved.

A computationally efficient algorithm for space-time block decoding

This paper presents a computationally efficient, low-power algorithm for the decoding of space-time block codes using a previously reported maximum likelihood algorithm (Tarokh et al. 1998). The new algorithm arrives at the same decision with less computation, and therefore reduces power dissipation for an actual implementation. Based on the previous algorithm, we develop a more efficient algorithm by utilizing the properties of the constellation signals and reported decision metrics. In most cases, the new algorithm results in more than 50% reduction in the computation complexity. The algorithm is illustrated for BPSK, QPSK, PSK or QAM.

A computationally efficient selective node updating scheme for decoding of LDPC codes

In this paper, we introduce a computationally efficient selective node update algorithm for the decoding of low-density parity check codes. Unlike the standard sum-product algorithm, where all bit and check nodes are updated at each decoding iteration, the developed algorithm only updates unreliable check and bit nodes. A simple reliability criteria is developed to determine the active bit and check nodes per decoding iteration. Based on the developed technique, significant computation reductions are achieved with very little or no loss in the BER performance of the LDPC codes. At a WER of 10-5 , 91.8% and 72.7% check node and 80% and 41% bit node computation reductions are obtained for a (96, 48) and a (504, 252) LDPC code, respectively. The proposed method can be implemented with a slight modification to the standard sum-product decoding algorithm with negligible additional hardware complexity. From a hardware point of view, the proposed algorithm offers power reductions proportional to the computation savings and it leads to higher decoding speeds in serial implementations by decreasing the number of required memory accesses

A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-/spl mu/m CMOS technology and occupies a core area of 0.25 mm/sup 2/. The ASIC architecture is highly scalable and can implement 2 /spl times/ 2, 8 /spl times/ 3, and 8 /spl times/ 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 /spl times/ 2 BPSK systems to 1.89 mW for 8 /spl times/ 4 16-QAM systems.

Computationally efficient ASIC implementation of space-time block decoding

In this paper, we describe a computationally efficient ASIC design that leads to a highly efficient power and area implementation of space-time block decoder compared to a direct implementation of the original algorithm. Our study analyzes alternative methods of evaluating as well as implementing the previously reported maximum likelihood algorithms (Tarokh et al. 1998) for a more favorable hardware design. In our previous study (Cavus et al. 2001), after defining some intermediate variables at the algorithm level, highly computationally efficient decoding approaches, namely sign and double-sign methods, are developed and their effectiveness are illustrated for 2x2, 8x3 and 8x4 systems using BPSK, QPSK, 8-PSK, or 16-QAM modulation. In this work, alternative architectures for the decoder implementation are investigated and an implementation having a low computation approach is proposed. The applied techniques at the higher algorithm and architectural levels lead to a substantial simplification of the hardware architecture and significantly reduced power consumption. The proposed architecture is being fabricated in TSMC 0.18 μ process.

Design of a system solution that modernizes legacy supervisory control and data acquisition systems as an early detection system

Background In industrial disasters, early detection of problems and crisis management are critical for saving the lives of people and reducing the impact of disasters. Purpose In this study, we design a special gateway system that bridges the gap between different communication protocols and enables legacy supervisory control and data acquisition systems to function early detection systems for potential industrial disasters. Methods The system uses a new queue mechanism to substantially improve the problem of data loss found in conventional supervisory control and data acquisition systems and utilizes identification (ID) prioritization to enable early detection of problems. The proposed system is implemented and tested on a Linux-based, 3G-capable Modbus gateway system. Modbus is used as the communication protocol and 3G technology is utilized to provide high-speed wireless data transfer components. The Modbus gateway device uses an ARM-based EP9302 processor and has digital input/output, relay outputs, and RS485 outputs. Conclusion This study is significant as it is the first work to show the application of the priority query execution method for Modbus gateway devices.

Design of frequency upconversion and downconversion blocks for 240 GHz communication systems

In this study, a communication system with 10 Gbps data rate is designed and its performance is investigated by using OOK (On-Off Keying) modulation in the 240 GHz band. OOK Modulation is carried out in a relatively low frequency band and is transported to the targeted high frequency band. The frequency downconversion is achieved by multiplying the generated local oscillator signal by the carrier signal from the communication channel. The downconverted signal is demodulated and the recovered signal is observed.

FPGA implementation of layered low density parity check error correction codes

In this study, Layered Low Density Parity Check (LDPC) Decoder algorithm in Error Correction Codes is implemented on FPGA. Firstly, Layered LDPC Decoder algorithm is designed with floating point in MATLAB, then fixed point model is developed. By testing Floating and Fixed point designs, transmitted information that is deformed by AWGN model is corrected by decoding iteratively. After this step, fixed point design is modelled in Verilog HDL. The design in Verilog HDL is matched with MATLAB model and then the Verilog HDL model is implemented on Xilinx Virtex 7 FPGA. Design that is implemented on FPGA has 280 MHz clock frequency and 25.426 Mbps data speed.