Erdal Oruklu

System-on-chip design for ultrasonic target detection using split-spectrum processing and neural networks

Ultrasonic detection and characterization of targets concealed by scattering noise is remarkably challenging. In this study, a neural network (NN) coupled to split-spectrum processing (SSP) is examined for target echo visibility enhancement using experimental measurements with input signal-to-noise ratio around 0 dB. The SSP-NN target detection system is trainable and consequently is capable of improving the target-to-clutter ratio by an average of 40 dB. The proposed system is exceptionally robust and outperforms the conventional techniques such as minimum, median, average, geometric mean, and polarity threshold detectors. For realtime imaging applications, a field-programmable gate array (FPGA)-based hardware platform is designed for system-onchip (SoC) realization of the SSP-NN target detection system. This platform is a hardware/software co-design system using parallel and pipelined multiplications and additions for highspeed operation and high computational throughput.

Fast Chirplet Transform With FPGA-Based Implementation

This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

Ultrasonic flaw detection using discrete wavelet transform for NDE applications

In this work, we analyze signal decomposition properties of discrete wavelet transform (DWT) for enhanced ultrasonic flaw detection. In wavelet signal decomposition, a collection of time-frequency representations of the signal with different resolutions is obtained. DWT allows to utilize both time and frequency domain information for compacting and decorrelating the flaw echo from clutter echoes. In this paper, we present the performance analysis of different wavelet kernels with respect to ultrasonic NDE applications and develop the wavelet selection criteria for optimal flaw detection. Experimental results indicate that DWT based flaw detection algorithms offer flaw-to-clutter ratio enhancement of 5-12 dB when the measured flaw-to-clutter ratio is 0 dB or less. DWT flaw detection system can be implemented efficiently for real time applications using reconfigurable architecture and lifting scheme.

FPGA-Based Configurable Frequency-Diverse Ultrasonic Target-Detection System

In this paper, we present field-programmable gate-array (FPGA)-based configurable architectures that are able to perform frequency-diverse target detection for real-time ultrasonic imaging. Three design methodologies are explored including the execution of the detection algorithm on an embedded microprocessor, the creation of a dedicated hardware solution, and the use of hardware/software codesign principles. In addition to the design flow, this paper presents the impact of parameter changes on the detection-algorithm performance and FPGA implementation results. Experimental studies show that the proposed configurable systems are able to meet real-time operation requirements, and the algorithm performs robustly.

3D image reconstruction and human body tracking using stereo vision and Kinect technology

Kinect is a recent technology used for motion detection and human body tracking designed for a video game console. In this study, we explore two different types of 3D image reconstruction methods to achieve a new method for faster and higher quality 3D images. Generating depth perception information using high quality stereo image textures is computationally heavy and inefficient. On the other hand, depth information can be obtained very fast using Kinect but the overall 3D image quality is not refined and it is low resolution. Thus, in this study we explore the combination of higher quality images on a webcam and faster computation of depth information on Kinect in order to create an efficient and enhanced 3D image reconstruction system. This high resolution system has a broad range of applications including 3D motion sensing of human body, hands tracking and finger gestures.

Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder

The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18mu technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.

Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging

Ultrasonic imaging algorithms, including detection and compression, are computationally complex and difficult to implement in hardware for real-time applications. In this paper, we present an ultrasonic reconfigurable subband decomposition processor (RSDP) that can employ wavelet filters for frequency diverse signal processing. This architecture enables parallel implementation of a lifting-based discrete wavelet transform. The configurability of the architecture applies to the selection of wavelet kernels and scales for subband decomposition, thresholding operation for compression, and the postprocessing detection algorithm. The underlying hardware design makes use of the fact that both compression and detection applications share the same algorithm fundamentals. A unified architecture has been designed that implements signal decomposition and reconstruction with forward and inverse discrete wavelet transforms. After the forward transform step, a windowing operation is applied to discriminate frequency bands for target detection. Using the same architecture, a thresholding operation is applied to wavelet coefficients for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications. The resulting architecture is adaptable, fast, and suitable for a system-on-a-chip implementation that requires minimal logic resources.

An Efficient FFT Engine With Reduced Addressing Logic

In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 N-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 mum technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.

Reduced memory architecture for CORDIC-based FFT

In this paper, a new pipelined, reduced memory CORDIC-based architecture is presented for any radix size FFT. A multi-bank memory structure and the corresponding addressing scheme are used to realize the parallel and in-place data accesses. The proposed memory-reduced CORDIC algorithm eliminates the need for storing twiddle factors and angles, resulting in significant area savings with no negative impact on performance. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic.

Hilbert transform pitfalls and solutions for ultrasonic NDE applications

Hilbert transform (HT) is a classical tool used to obtain complex analytical signal representation, which is useful for instantaneous frequency and envelop estimation of bandpass signals. However, noise has a significant adverse impact on the performance of HT. Furthermore, the narrowband signal condition in Bedrosian identity makes it problematic to analyze ultrasonic scattering signal using HT. In this investigation, two key issues related to Hilbert transform are addressed for enhanced instantaneous frequency (IF) estimation. First, in order to minimize the effect of the noise, ultrasonic signals are decomposed to multiple narrowbands and instantaneous frequencies within these bands are estimated. Second, a weighted estimated of IF based on envelop estimate of each narrowband is introduced. These methods are applied to various experimental ultrasonic data sets and utilized to examine microstructure scattering, effects of attenuation in large grained materials, and flaw detection in presence of high scattering noise. Simulation studies and experimental results support accuracy of the IF estimation. Enhanced IF estimation techniques provide tractable frequency estimation and makes it possible to quantify spectral shifts due to attenuation, scattering and dispersion effects.