Eric Belhaire

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAMs further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

Spin-MTJ based Non-volatile Flip-Flop

Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.

TAS-MRAM based Non-volatile FPGA logic circuit

As one of the most promising spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. The integration of MRAM in FPGA allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, easily realize the dynamical reconfiguration and multi-context configuration. However, the conventional MRAM technology based on field induced magnetic switching (FIMS) writing approach consumes very high power and large circuit surface, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAMs further development in memory and logic circuit. Thermally assisted switching (TAS) based MRAM is then evaluated to address these issues and some design techniques for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90 nm technology, some chip characteristic results have been calculated to demonstrate the expected performance of TAS-MRAM based FPGA logic circuits.

Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.

Spintronic Device Based Non-volatile Low Standby Power SRAM

SRAM is an indispensable component in modern microprocessors to store copies of the most frequently used data from the main memory. The high write/read speed of SRAM assures the desired memory throughput required by the internal high operating frequency of the microprocessor. However SRAM memory is volatile, which causes some drawbacks for computer systems such as high standby power and low data security etc. Spintronic devices as magnetic tunnel junction (MTJ) features non-volatility, high write/read speed and exhibits good interface with CMOS. They have therefore the potential to overcome the SRAM limitations. In this paper, we present a Non-Volatile SRAM that combines MTJ devices with classical SRAM. Used in a microprocessor, it can ldquosnapshotrdquo the currently-executing program and data from SRAM to the relating MTJ cells at regular intervals. If its power supply is interrupted, this self-checkpointing processor can near-instantly (~700 ps) restore its state from the last checkpoint, allowing it to resume execution with little loss of progress. The non-volatility of MTJ and the high data recovering speed allows the NVSRAM to consume nearly zero standby power.

High-current large-bandwidth photosensor on standard CMOS processes

On standard CMOS processes, basically two photosensors may be designed: photodiodes or vertical bipolar phototransistors. A trade-off must be found between the area of the sensor, its sensitivity and its bandwidth. In most designs, the high sensitivity of the sensor is a key point and led to choosing a phototransistor based solution. However this choice is made at the expense of the bandwidth of the sensor. For small currents, an analysis shows that it is mainly proportional to the base-emitter capacitance Cbe and to the collector current. Hence, in the case of a floating base bipolar and for a given current, the only way of reducing Cbe is to decrease the emitter area. On the other hand, the sensitivity is to be preserved. We have proposed and tested an original sensor based on the splitting of phototransistors. The basic idea is to use minimum size emitter bipolar transistors and to increase their collector-base junction perimeter. Thanks to this design, for a given sensor area, the bandwidth has been improved by a factor of 3 and the sensitivity has been preserved. This solution has been successfully used on an operational retina performing stochastic computations at video rates. In particular, thanks to our design, we have been able to successfully implement a 150 by 50 micrometer2 optoelectronic random generator providing up to 100,000 random variables per second.

VHDL Simulation of Magnetic Domain Wall Logic

The VHSIC hardware description language (VHDL) simulation of domain wall logic allows to validate magnetic circuits functionality early in the design stage. In this paper, we present two VHDL simulation techniques for domain wall (DW) logic. The first one, closer to the physics, uses models of components described at the behavioral level. It allows to study the basic functions and reveals the specificities of DW logic. The second one, closer to the logic, models components with logic gates and delays and it allows very fast simulation of complex circuits

An optoelectronic CMOS circuit implementing a simulated annealing algorithm

An original optoelectronic implementation of simulated annealing is presented. A compact and simple optical system provides a chip with arrays of independent random noise sources. The silicon chip is composed of a mesh of computing cells. Each cell includes both analog and digital circuits and includes two photosensors. A detailed analysis of this cell is given including a presentation of the design constraints. A 4/spl times/4-cells prototype chip was implemented in a 1 /spl mu/m CMOS digital technology and was successfully operated at 20000 iterations per second. The measurements and characterization of this chip made possible the successful design of a 600-cells chip also presented. These results demonstrate the video-rate application of simulated annealing to early vision tasks.

Two analog counters for neural network implementation

Analog counters are an attractive building block for Artificial Neural Networks circuits, either for weight representation or for statistical learning algorithms. We give two schemes for such counters, which feature different design trade offs. Model, simulation and test results are presented.

FPN Sources in Bolometric Infrared Detectors

Low manufacturing cost and ease of use favor spreading of 2-D bolometric infrared detector arrays over various application domains such as predictive maintenance, medical imaging, automotive industry, and security. The infrared detectors main figure of merit has long been the noise equivalent temperature difference (NETD), which sets the minimum temperature difference distinguishable from background noise at sensor output. However, while nowadays uncooled detectors have achieved sufficient NETD, fixed pattern noise (FPN) is indeed becoming a crucial figure of merit especially when the focal plane array (FPA) is not regulated by a thermoelectric cooler (TEC). In this paper, we study the various sources of dispersion of infrared bolometric detectors and their respective impact on FPN in the resulting image. We propose an analytical model to identify main sources of nonuniformity, and the confrontation of results with actual measurements leads to the ability of a highly accurate on-chip thermal drift compensation.