Eric C. Harley

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

Observation of semiconductor device channel strain using in-line high resolution X-ray diffraction

In-line high resolution X-ray diffraction has been used to analyze embedded silicon-germanium (eSiGe) epitaxially grown in the source/drain regions of complementary metal-oxide-semiconductor devices. Compared to blanket films, the diffraction from patterned devices exhibited distinct features corresponding to the eSiGe in the source/drain regions and Si under the gate and SiGe. The diffraction features modulated with structural changes, alloy composition, and subsequent thermal processing. Reciprocal space measurements taken around the (224) diffraction peak revealed both in-plane (h) and out-of-plane (l) lattice deformation, along with features corresponding to the regular spacing between the gates.

On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi:C strain. Acknowledgements This work was performed by IBM/AMD/Freescale Alliance Teams at various IBM Research and Development Facilities. We wish to thank Applied Materials and ASM America for supplying high quality eSi:C EPI materials. References: [1] Kah-Wee Ang, King-Jien Chui, Vladimir Bliznetsov, Yihua Wang, Lai-Yin Wong, Chih-Hang Tung, N. Balasubramanian, Ming-Fu Li, Ganesh Samudra, and Yee-Chia Yeo, IEDM Tech. Dig., p503, 2005.[2] Yaocheng Liu, Oleg Gluschenkov, Jinghong Li, Anita Madan, Ahmet Ozcan, Byeong Kim, Tom Dyer, Ashima Chakravarti, Kevin Chan, Christian Lavoie, Irene Popova, Teresa Pinto, Nivo Rovedo, Zhijiong Luo, Rainer Loesing, William Henson, Ken Rim, Symp. on VLSI Tech., p.44, 2007. [3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, B. White, SOI Conf. Proc., p.17, 2007. [4] Zhibin Ren, G. Pei, J. Li, F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J. W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, I. Lauer, D.-G. Park, D. Sadana, and G. Shahidi, Symp. on VLSI Tech., P. 172-173, 2008. [5] A. Madan, J. Li, Z. Ren, F. Yang, E. Harley, T. Adam, R. Loesing, Z. Zhu, T. Pinto, A. Chakravarti, A. Dube, R. Takalkar, J. W. Weijtmans, L. Black, D. Schepis, ECS SiGe and Realted Materials and Devices Symposium, Hawaii, Oct. 2008 (to be published).

Control of Epitaxial Growth of SiGe

Silicon-Germanium (SiGe), used to boost pFET performance and enhance the properties of high-k metal gate devices, is grown by selective epitaxy on silicon. Since device parameters depend critically on the deposited SiGe thickness, we apply several advanced techniques to control deposition. Feedback and feed-forward of growth rate data is used to control deposition tools. We also apply a pattern-density based predictive growth rate, since pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. We use run to run analysis of deposition data and a feature of the deposition tool to tune cross wafer deposition rates for optimized uniformity. Finally, we consider local (within chip) growth rate variation. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip.

First time right deposition of embedded SiGe in new products

Embedded SiGe, used to boost pFET performance, is grown by selective epitaxy on silicon. Pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. Since device control depends critically on thickness, we apply a pattern-density based predictive growth rate, which is used as input for the existing advanced process control method. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip.

Effect of Ion Implantation and Anneals on Fully-strained SiC and SiC:P Films using Multiple Characterization Techniques

In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement [1-3]. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. μXRD strain measurements and SIMS (C and P content) were performed on reference test macros on patterned lithographic wafers. μXRD strain measurements (related to substitutional C) of the asdeposited SiC films show that the C is lower than the actual C suggesting that there is interstitial C in the film. After M1 device measurements, Nanobeam Diffraction (NBD) analysis to determine channel strain was done on selected samples. An in-line μXRD system was used to monitor the strain and thickness variation of the SiC stressor with critical processing steps. Typical uXRD measurements demonstrate that there is a depth profile for the crystalline integrity of the SiC stressor films. The top surface which is in the implant range shows no strain (amorphization due to implants) compared to the fully strained, deeper regions (Fig 1). Figure 2 shows a typical cross-sectional TEM image and NBD patterns with the as-deposited SiC embedded in the source and drain. After M1 device measurements, good correlation was seen between the NBD and uXRD measurements (Fig 3). Stressor strain for samples 1-4 was retained after complete processing. Sample 5 which saw a high temperature anneal showed a complete loss of strain. This correlated well with the device results [4]. Full characterization has helped identify process integration schemes which give significant drive current enhancements [4].