Éric Imbernon
Centre national de la recherche scientifique
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Publication
Featured researches published by Éric Imbernon.
bipolar/bicmos circuits and technology meeting | 2005
Isabelle Bertrand; Vasanta Pathirana; Éric Imbernon; Florin Udrea; Marise Bafleur; Ranick Ng; Hugues Granier; Bernard Rousset; Jean-Marie Dilhac
In this paper, we present new lateral DMOS and IGBT structures based on a partial SOI substrate. The partial SOI substrate, formed through LEGO recrystallization process improves considerably the breakdown capability and the thermal behavior of these devices compared to full SOI devices. Experimental results of high voltage power devices implemented on such a process are presented for the first time.
international symposium on power semiconductor devices and ic s | 2003
Jean-Louis Sanchez; E. Scheid; Patrick Austin; M. Breil; H. Carriere; P. Dubreuil; Éric Imbernon; F. Rossel; B. Rousset
P/sup +/ walls through wafer can be considered as a region key in the 3D architecture of new bi-directional current and voltage power integrated devices. In this paper, we demonstrate the possibility of fabricating these P/sup +/ walls combining the deep RIE of silicon and deposit of boron doped polysilicon.
international semiconductor conference | 2001
Éric Imbernon; J. L. Sanchez; Patrick Austin; Marie Breil; Olivier Causse; Bernard Rousset; Françoise Rossel
In this paper, a flexible technological process suitable for the development of complex integrated power structures based on the functional integration mode is presented. This technological process is based on a succession of basic technological steps corresponding to the fabrication of IGBT devices and compatible specific steps supporting more complex functions.
bipolar/bicmos circuits and technology meeting | 2004
C. Caramel; P. Austin; J.-L. Sanchez; Éric Imbernon; M. Breil
In this paper, we present a new integrated structure which can protect insulated gate power devices (lGBT, MMOS, EST, ... ) from short-circuit operating mode. This strnctnre is built with an anode voltage sensor, a delay LDMOS transistor, a LDMOS transistor allowing the power device gate unload and a Zener diode. It is notable that this protection structure is fully compatible with a power device technological process. The operating mode and the flrst optimization of the protection structure are presented. For this, IGBT is used as test device. 2D simulations are performed with ISE TCAD. First experimental results of the anode voltage sensor are given and compared with simulation results.
Proceedings of SPIE | 2004
Jean-Louis Sanchez; E. Scheid; Patrick Austin; M. Breil; H. Carriere; P. Dubreuil; Éric Imbernon; F. Rossel; Bernard Rousset
P+ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P+ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P+ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.
Revue internationale de génie électrique | 2009
Florence Capy; Marie Breil; Frédéric Richardeau; Éric Imbernon; Jean Pierre Laur; J. L. Sanchez
In this paper, a detailed analysis of the new monolithically integrated power device dedicated for self switching converters is carried out. This new functionality, based on the functional integration concept, integrates within a silicon die protection functions, self-control and a power switch. The originality of the device resides in its dynamic behaviour. The device uses a new type of switching mode: the self-switching, which includes protection within the switching process . The analyses of the device operating principles as well as the optimization steps rely on 2D physical simulations.
international symposium on power semiconductor devices and ic's | 2006
C. Caramel; Patrick Austin; Jean-Louis Sanchez; Éric Imbernon; Bernard Rousset
One of the steps of the power components reliability improvement is to integrate protection structures (Robb, 1994 and Yeki, 1994). An integrated structure which protect IGBT against short-circuit conditions has already been studied. This structure has been studied and improved for its integration in a classical IGBT technological process (Caramel, 2006). Generally, the integration of protection structures and power devices on the same substrate leads to insulation problems. In order to overcome these problems for our application, we propose in these paper three insulation techniques compatible with a classical IGBT technological process. [2D] numerical simulations have been thus performed in order to highlight the necessity of insulation and for compare the insulation techniques efficiency
PESM 2014 (Plasma Etch and Strip in Microtechnology) | 2014
Aurélie Lecestre; Pascal Dubreuil; Sylvain Noblecourt; Josiane Tasselli; Éric Imbernon; Frédéric Morancho
Archive | 2018
Éric Imbernon; Jean-Christophe Marrot
Archive | 2018
Hugues Granier; Alexandre Arnoult; David Bourrier; Laurent Bouscayrol; Pierre-François Calmon; F. Carcenac; Samuel Charlot; René-David Colin; Véronique Conédéra; Rémi Courson; E. Daran; Monique Dilhan; Thierry Do Conto; Jean-Baptiste Doucet; Pascal Dubreuil; Quentin Gravelier; Éric Imbernon; Adrian Laborde; Guy Lacoste; Nathalie Lauber; Alexandre Lauvergne; Aurélie Lecestre; Guillaume Libaude; Vinciane Luque; Antoine Maiorano; Jean-Christophe Marrot; Laurent Mazenq; Fabien Mesnilgrente; Benjamin Reig; Bernard Rousset