Eric K. Hall

Design and analysis of turbo codes on Rayleigh fading channels

The performance of turbo codes using coherent BSPK signaling on Rayleigh fading channels is considered. In regions of low signal-to-noise, performance analysis uses simulations of typical turbo coding systems. For higher signal-to-noise regions beyond simulation capabilities, an average upper bound is used, where the average is over all possible interleaving schemes. Fully-interleaved and exponentially-correlated Rayleigh channels are explored. Furthermore, the design issues relevant to turbo codes are explored for the correlated fading channel.

Analysis and Design of Moderate Length Regular LDPC Codes with Low Error Floors

The traditional method to estimate code performance in the higher SNR region is to use a sum of the contributions of the most dominant error events to the probability of error. If an ML decoder is used, these events will be minimum distance codewords; the traditional decoder used in LDPC codes, some variant of the message passing algorithm, will introduce non-codeword error events known as trapping sets. For long LDPC codes it is difficult to enumerate all of these dominant error events. A procedure to efficiently find dominant error events by using the regular low-density structure of an LDPC code is presented here. The search method can be adapted to work with LDPC codes of various regular and irregular degree distributions, but is especially suited to a very practical subset of LDPC known as regular {3, 6} codes of moderate block length. We also show how codes with very low error floors can be created by utilizing this search method.

Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design

A novel high-throughput (6 Gb/s), fully-parallel FPGA-based 1200-bit rate-1/2 Low Density Parity Check (LDPC) decoder design is presented. The decoder features a PEG- based regular (6,3) code and a modified min-sum algorithm that improves performance without any additional hardware overhead.

Efficient quantization schemes for LDPC decoders

LDPC codes have attracted much attention recently for their near-capacity performance and high throughput owing to parallel decoding architectures. While simulations are normally done with floating point computation, any practical implementation (ASIC or FPGA) will be built with fixed-point computation. Obviously, decoder speed will increase, and resource requirements will drop, with low-precision implementations, say 3,4, or 5-bit architectures. In this paper we study the effects of quantization in this regime, using density evolution and decoder simulation. Detailed sum-product decoder implementations are given, and performance losses relative to floating point decoding are given. In particular, 4-bit decoder architectures sustain only 0.1 dB penalty.

Stream-oriented turbo codes

A stream-oriented parallel concatenated convolutional (turbo) code (PCCC) is examined. The stream encoder uses continuous encoding with the the interleaver(s) viewed as a finite state permuters (FSPs). With this encoding architecture, block interleaver design is reexamined and convolutional interleavers are considered. Decoding is performed using a pipelined architecture where each constituent decoder uses a continuous version of the symbol-by-symbol MAP decoding algorithm. Performance and implementation issues are discussed and comparisons made to the traditional block decoding architecture. Finally, stream PCCC design using convolutional interleavers is examined based on performance and implementation.

Convolutional interleavers for stream-oriented parallel concatenated convolutional codes

The design of convolutional interleavers (CIs) is considered for a stream-oriented parallel concatenated convolutional coding (PCCC). Design rules are developed for CIs using analysis of the interleaving equations as well as simulation results. Results show that CIs are viable design options which can offer improved performance for low latency designs as well as implementation advantages for PCCC.

Stream-oriented parallel concatenated convolutional codes

A stream-oriented parallel concatenated convolutional (turbo) code (PCCC) is examined. The stream encoder uses continuous encoding with an interleaver constructed with using a tapped delay line. Stream decoding is envisioned using a pipeline of continuous decoding modules. The performance of the stream PCCC is examined and compared to a block-oriented scheme. The block interleaver design is addressed for continuous encoding and a class of non-block interleavers termed convolutional interleavers are considered.

AISR Missions on Intelsat EpicNG Ku-Band

Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR) systems currently rely heavily on transponded satellites, both military and commercial at X-, Ku- and Ka-bands, for missions requiring beyond line of sight connectivity. Ku-band commercial satellites are the work-horse for both manned and unmanned Airborne ISR (AISR) operations today. In the future, C4ISR systems will require higher throughput, greater protection and improved affordability to align with future mission needs, mitigate threats, and fit within budgetary constraints. Intelsat EpicNG satellites provide cost-effective, next-generation, Ku-band capabilities including spot beams, higher throughput, improved efficiencies, and protection using deployed infrastructure. In this paper, the EpicNG architecture is described with comparisons to the legacy Ku-band systems and its application to the unique performance and mobility management needs of AISR systems. A detailed performance analysis is presented using representative AISR systems against a set of manned and unmanned mission/platform scenarios, with comparisons to legacy Ku-band and WGS Ka-band performance. It is shown that the EpicNG Ku-band constellation offers unique performance and affordability opportunities for AISR missions and enables the next generation military Ku/Ka-band C4ISR infrastructure.