Erik F. Dirkx

Scheduling and admission control policies: a case study for ATM

Scheduling mechanisms and admission policies play an important role in optimising resource allocation in networks offering integrated services. The scheduler mediates the low-level contention for service between cells of different classes, while admission control regulates the acceptance or blocking of incoming traffic on a connection-by-connection basis. These two levels of control are of course closely related in the sense that if too much traffic is allowed to enter the network by an overly lax admission control policy, then no scheduler will be able to provide the requested Quality of Service (QoS) for all traffic classes. A functioning admission control is a prerequisite for any guarantee of cell-level QoS while its merit is to guarantee QoS efficiently and fairly. We focus on an ATM switch to demonstrate these principles.

Adaptive load balancing of parallel applications with multi-agent reinforcement learning on heterogeneous systems

We report on the improvements that can be achieved by applying machine learning techniques, in particular reinforcement learning, for the dynamic load balancing of parallel applications. The applications being considered in this paper are coarse grain data intensive applications. Such applications put high pressure on the interconnect of the hardware. Synchronization and load balancing in complex, heterogeneous networks need fast, flexible, adaptive load balancing algorithms. Viewing a parallel application as a one-state coordination game in the framework of multi-agent reinforcement learning, and by using a recently introduced multi-agent exploration technique, we are able to improve upon the classic job farming approach. The improvements are achieved with limited computation and communication overhead.

A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-II Pro FPGAs

Today, the technology is available for the creation of dynamically self-reconfigurable systems. However, the lack of efficient methodologies for customizing the system to the requirements of the application withholds the widespread use of this promising technique. This paper fills the existing design productivity gap concerning dynamically self-reconfigurable systems on chip by proposing a consistent framework for the toolflow that will lead, in a very cost effective way, to an RT level implementation of this type of systems. As a proof of concept we discuss a case study where a virtual instrumentation machine for DSP applications is implemented on a Virtex-II Pro component and where the reconfiguration process is controlled by an embedded processor

Causal analysis for performance modeling of computer programs

Causal modeling and the accompanying learning algorithms provide useful extensions for in-depth statistical investigation and automation of performance modeling. We enlarged the scope of existing causal structure learning algorithms by using the form-free information-theoretic concept of mutual information and by introducing the complexity criterion for selecting direct relations among equivalent relations. The underlying probability distribution of experimental data is estimated by kernel density estimation. We then reported on the benefits of a dependency analysis and the decompositional capacities of causal models. Useful qualitative models, providing insight into the role of every performance factor, were inferred from experimental data. This paper reports on the results for a LU decomposition algorithm and on the study of the parameter sensitivity of the Kakadu implementation of the JPEG-2000 standard. Next, the analysis was used to search for generic performance characteristics of the applications.

Analysis of large ATM switches using a platform-independent simulation environment

This paper presents a general simulation approach applied to the problem of performance evaluation of large switching fabrics. Experimental results in the form of cell queuing delay and buffer occupancy distributions for switches with up to 2048 inputs and outputs operating under a wide variety of loads are presented. The traditional dilemma between simulation model validity and its run-time where a more general purpose model inevitably results in longer execution times, is eliminated by the introduction of a new parameter: the architecture of the simulation platform. With model validity as an invariant, the simulation platform can range from a sequential computer via shared memory and distributed memory general purpose parallel processors up to a dedicated emulator, on the condition that the software engineering problem has been solved, i.e. that there is a software tool available that automates that task of generating simulation code for various platforms from a single model, taking the characteristics of the platforms (granularity) into account. An analytical model of the class of applications under study gives insight into the influence of machine and problem parameters on simulator run-time performance. Examples of its use for the choice of an optimal parallel architecture for a given problem and of its use for the estimation of application behavior on a given parallel machine architecture are presented.

The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators

To accelerate a sequential discrete event simulator it is necessary to accelerate the used priority queue algorithm. In first order the used priority queue algorithm must be performant. A hardware implementation of the algorithm will lead to an important acceleration. FPL technology is used to implement a co-processor, that can manage the Fishspear priority queue algorithm efficiently by exploiting parallelism and pipelining. This is achieved by using an MIMD ALU architecture and the concepts action oriented programming,pre-condition evaluation and hierarchical divided state-machine.

An animated simulation environment for microprocessors

Abstract The dynamic observation of the state of a process while it executes is very helpful to give insight into the operation of a computer, and hints about causes of malfunction. Traditional teaching and debugging tools used to trace program execution give unfortunately very limited access to the state of a process by just displaying a few of the processor registers. An instruction set processor simulator build at the ‘Vrije Universiteit Brussel’ uses a multi-window users-interface to give its operator a more complete view of the state of the process that is executed on the simulated processor. This paper details the motivations for the project, its present status, and some of the technical aspects of its realization.

Modeling the Performance of Communication Schemes on Network Topologies

This paper investigates the influence of the interconnection network topology of a parallel system on the delivery time of an ensemble of messages, called the communication scheme. More specifically, we focus on the impact on the performance of structure in network topology and communication scheme. We introduce causal structure learning algorithms for the modeling of the communication time. The experimental data, from which the models are learned automatically, is retrieved from simulations. The qualitative models provide insight about which and how variables influence the communication performance. Next, a generic property is defined which characterizes the performance of individual communication schemes and network topologies. The property allows the accurate quantitative prediction of the runtime of random communication on random topologies. However, when either communication scheme or network topology exhibit regularities the prediction can become very inaccurate. The causal models can also differ qualitatively and quantitatively. Each combination of communication scheme regularity type, e.g. a one-to-all broadcast, and network topology regularity type, e.g. torus, possibly results in a different model which is based on different characteristics.

Scalable Run Time Reconfigurable Architecture

Currently multi-FPGA reconfigurable computing systems are still commonly used for accelerating algorithms. This technology where acceleration is achieved by spatial implementation of an algorithm in reconfigurable hardware has proven to be feasible. However, the best suiting algorithms are those who are very structured, can benefit from deep pipelining and need only local communication resources. Many algorithms can not fulfil the third requirement once the problem size grows and multi-FPGA systems become necessary. In this paper we address the emulation of a run time reconfigurable processor architecture, which scales better for this kind of computing problems.

Parallel Discrete Event Simulation: Opportunities and Pitfalls

Discrete event models are used in a wide variety of applications, ranging from flexible manufacturing systems to digital electronics. A common feature to all these domains is the complexity of the systems under investigation. In general, detailed models of real size designs are analytically intractable and numerically prohibitive to evaluate. Discrete event simulation is one possibility to gain insight in the behaviour and performance characteristics of complex systems. However, the lack of efficient simulation tools makes discrete event simulation of large systems excessively slow on conventional computers. This fundamental problem can be addressed according to two different strategies: an adaptation of the simulation model and the utilization of more powerful computers. In this paper, an overview of various approaches of the second class to upspeed discrete event simulation is given. It is shown that the traditional sequential simulation algorithm cannot be parallellized, in order to take advantage of opportunities offered by parallel computer architectures. It will be indicated that in order to obtain a performance gain in terms of the only realistic benchmark possible, a sequential simulation on a single processor, careful tuning is required in order to match software requirements with hardware resources. The most important parameters of this problem will be highlighted.