Erik J. Brandon

Flexible substrate micro-crystalline silicon and gated amorphous silicon strain sensors

We present two different kinds of semiconductor strain sensors: ungated n+ micro-crystalline silicon (n+ /spl mu/C-Si), and gated hydrogenated amorphous silicon (a-Si:H). Both sensor types are fabricated on flexible polyimide substrates. The sensors were characterized with bending perpendicular, parallel, and at 45/spl deg/ with respect to the sensor bias direction, and for several bending diameters. Sensor size and power consumption are significantly reduced compared to metallic foil strain sensors. Small sensor size and ease of integration with a-Si:H thin-film transistors also allows arrays of strain sensors or combinations of strain sensors with varying geometric orientation to allow strain direction as well as magnitude to be unambiguously determined.

Printed microinductors on flexible substrates for power applications

A low-profile microinductor was fabricated on a copper-clad polyimide substrate where the current carrying coils were patterned from the existing metallization layer and the magnetic core was printed using a magnetic ceramic-polymer composite material. Highly loaded ferrite-polymer composite materials were formulated, yielding adherent films with 4/spl pi/M/sub s//spl ap/3900 G at +5000 Oe applied DC field. These composite magnetic films combine many of the superior properties of high temperature ceramic magnetic materials with the inherent processibility of polymer thick films. Processing temperatures for the printed films were between 100/spl deg/C and 130/spl deg/C, facilitating integration with a wide range of substrates and components. The quality factor of the microinductor was found to peak at Q=18.5 near 10 MHz, within the optimal frequency range for power applications. A flat, nearly frequency independent inductance of 1.33 /spl mu/H was measured throughout this frequency range for a 5 mm/spl times/5 mm component, with a DC resistance of 2.6 /spl Omega/ and a resonant frequency of 124 MHz. The combination of printed ceramic composites with organic/polymer substrates enables new methods for embedding passive components and ultimately the integration of high Q inductors with standard integrated circuits for low profile power electronics.

Crystallographically Oriented Thin-Film Nanocrystalline Cathode Layers Prepared Without Exceeding 300°C

The highest capacity rf sputtered cathode layers created for use in thin-film solid-state batteries have been found to require an annealing step with temperatures in excess of 700°C. Since this high-temperature process step is incompatible with silicon device technology and flexible polymer substrates, the development of a low-process temperature (less than or equal to 300°C) cathode layer has been undertaken. Thin-film cathode layers consisting of LiCoO 2 were deposited using planar magnetron rf sputtering and subsequently incorporated into thin-film solid-state cells comprised of a LiPON electrolyte and lithium metal anode. Film composition was examined using Rutherford backscattering spectrometry and inductively coupled plasma mass spectroscopy, while phase content and crystal structure were studied through X-ray diffraction experiments conducted at the Stanford Synchrotron Radiation Laboratory. Microstructure and morphology were examined using transmission and scanning electron microscopy. It was found that LiCoO 2 could be deposited at room temperature in a nanocrystalline state with a defined (104) out of plane texture and a high degree of lattice distortion. By heating these layers to 300°C, the average grain size was increased while lattice distortion was minimized. Electrochemical cycling data revealed that the low temperature annealing step increases cell capacity to near theoretical values while significantly improving both the rate capability and discharge voltage. Impedance analysis on test cells showed that the electronic resistance of the cells is decreased after heating to 300°C.

Fabrication and characterization of microinductors for distributed power converters

Inductors play a key role in DC-DC converters, but few options exist for implementing on-chip inductors for highly miniaturized, monolithic power converters. Microinductors constructed by standard microelectronic fabrication techniques with magnetic films as the core material have been investigated during the past 20 years with mixed results. A 13-mm/sup 2/ microinductor based on a spiral geometry and having L = 3.2 /spl mu/H and Q = 1.3 at 1 MHz is reported here. Key issues regarding microinductor design and performance are discussed.

Carbon-based printed contacts for organic thin-film transistors

Organic thin-film transistors (OTFTs) employing a flexible, conductive carbon particle-polymer composite material for the drain-source ohmic contacts are reported herein. The contacts can be deposited using standard stencil printing techniques and are processed at low temperature, thereby facilitating their integration with heat sensitive substrates. The carbon contacts were stencil printed on a silicon dioxide gate dielectric layer, and the poly(3-hexylthiophene) semiconductor was deposited via solution casting from toluene. The OTFTs exhibited field-effect behavior over a range of drain-source and gate voltages, similar to devices employing deposited gold contacts.

Lithium micro-battery development at the Jet Propulsion Laboratory

Recent successes in the effort to miniaturize spacecraft components using MEMS technology, integrated passive components, and low power electronics have driven the need for very low power, low profile, low mass micro-power sources for micro/nanospacecraft applications. Recent work at JPL has focused upon developing thin film/micro-batteries compatible with temperature sensitive substrates. A process to prepare crystalline LiCoO/sub 2/ films with RF sputtering and moderate (<700/spl deg/C) annealing temperature has been developed. Thin film batteries with cathode films prepared with this process have specific capacities approaching the practical limit for LiCoO/sub 2/, with acceptable rate capabilities and discharge voltage profiles. Solid state micro-scale batteries have also been fabricated, with feature sizes on the order of 50 microns.

Flexible electronics for space applications

NASA is currently developing a host of deployable structures for the exploration of space. These include balloons, solar sails, space-borne telescopes and membrane-based synthetic aperture radar. Each of these applications is driven by the need for a thin, low mass, large area structure (i.e., polymer-based) which could not be implemented using conventional engineering materials such as metals and alloys. In each case, there is also the need to integrate sensing and control electronics within the structure. However, conventional silicon-based electronics are difficult to integrate with such large, thin structures, due to a variety of concerns including mass, reliability and manufacturing issues. Flexible electronics, particularly thin film transistors (TFTs), are a potentially key enabling technology that may allow the integration of a wide range of sensors and actuators into these types of structures. There are numerous challenges, however, regarding the survivability of such devices during stowage and deployment of the structure, as well as during operation in the harsh environments of space. We have fabricated TFTs on polyimide substrates, and are investigating the durability of these devices with respect to relevant space environments. We are also developing flexible sensor technologies for the integration of distributed sensor networks on large area structures.

Double-Layer Capacitor Electrolytes Using 1,3-Dioxolane for Low Temperature Operation

Double-layer capacitor electrolytes employing 1,3-dioxolane as a cosolvent with acetonitrile have been evaluated in coin cells using electrochemical impedance spectroscopy and dc charging and discharging tests. Addition of the lower-melting-point 1,3-dioxolane to the standard acetonitrile solvent was found to extend the low-temperature operational range of test cells beyond that of commercially available cells. By adjusting the concentration of the tetraethylammonium tetrafluoroborate salt used, the equivalent series resistance can be minimized to enable optimal power delivery at a given temperature.

Power Management and Distribution for System on a Chip for Space Applications

In this paper a method for achieving integrated power electronics is discussed. Future spacecraft are projected to feature high levels of integration at the system level (i.e., a “systems on a chip” approach) particularly in areas not typically associated with an integrated approach (such as inertial reference systems, RF communications, imaging, sensors, etc.). Taking full advantage of the miniaturization occurring in these other systems will require commensurate reductions in the size of the power electronics. Power electronics are traditionally larger due to the need for high value passive components requiring significant power handling capabilities. Our approach takes advantage of lower projected power requirements and utilizes integrated, on-chip passives and novel high voltage transistors to achieve adaptive distributed on-chip power management and distribution (PMAD). Operating from a single supply, this on-chip PMAD will operate at power levels of up to 1 W, at frequencies of 110 MHz. INTRODUCTION Integrated systems on future nanosatellites will get their supply voltage from a common power bus. These systems will rely on efficient adaptive on-chip power management circuits for generating the internal voltage levels necessary for operation of the sensors, actuators and other subsystems. For space applications, there are several challenges in building an efficient completely integrated power management system, including a) the development of a new generation of miniaturized large value passive components (inductors and capacitors) for DC-DC converter circuits that can be integrated on-chip, b) the development of on-chip power interrupt protection (such as microbatteries), c) the development of high voltage transistors that can coexist with traditional low voltage transistors in the same radiation hardened silicon substrate, and d) the development of a library of mixed-signal/mixedvoltage CMOS cells suitable for the construction of a completely integrated on-chip power management system. This paper summarizes JPL’s effort in overcoming the challenges of building a completely integrated power management system for future avionics microsystems for deep space applications for NASA. PMAD REQUIREMENTS FOR AVIONICS SYSTEM ON A CHIP Figure 1 shows the block diagram of a proposed on-chip adaptive power management system for the next generation of highly miniaturized satellites. Principle components in this on-chip power management system are switching DC-DC converters with large value onchip inductors and capacitors, micro batteries, battery charge/discharge circuits and digital 110 circuits for interface and control. Digital Interface Bus 12C Main Satellite Power Bus

Flexible substrate a-Si:H TFTs for space applications

We have fabricated hydrogenated amorphous silicon (a-Si:H) TFTs on Kapton/sup (R)/ polyimide flexible substrates and characterized their response to deployment-like mechanical stresses and to radiation exposure. To maintain substrate flatness and provide improved thermal transfer during fabrication, we used a pressure-sensitive silicone gel adhesive layer to mount Kapton/sup (R)/ substrates onto glass carriers. The test results, presented in this paper, are encouraging for space use of a-Si:H TFTs on polymeric substrates. Device function was retained even after 1 Mrad fast electron irradiation, and irradiation-induced device changes were removed by low-temperature thermal annealing. Although some TFTs were destroyed by substrate stressing, the majority survived with only small changes, suggesting that care in device design and placement may reduce or eliminate this problem.