Erik Maehle

DAMP—a dynamic reconfigurable multiprocessor system with a distributed switching network

In this paper the dynamic reconfigurable multiprocessor system DAMP is introduced which is currently under development at the University of Paderborn. Its architecture is based on a single type of building block (DAMP-module) consisting of a transputer, memory and a local switching network. These building blocks are interconnected according to a fixed topology with restricted neighborhood (octagonal torus). Circuit-switching is used to establish and to release communication paths between nodes dynamically during runtime under program control. Currently an 8-processor prototype is operational, a redesign for a 64-processor system is under way. After describing the basic architecture of the DAMP system the paper concentrates on its reconfiguration properties (especially blocking problems). Finally the implementations of centralized and decentralized switch control on the prototype system are presented and first measurements of communication setup times are discussed.

DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems

Abstract Monitoring tools are important parts of future programming environments for parallel computers. In this paper the software monitor DELTA-T is presented which has been developed for performance monitoring of (standard) multi-transputer systems at the University of Paderborn. Instrumentation is implemented by ‘spy’-processes which are inserted into the target system either to observe it at the node or at the process level. Measurement traces generated by these spies are buffered locally in the node memories. A global system view is achieved by time-stamping the recorded events with a globally valid system time. Evaluation is carried out offline on a host workstation either with an animation tool or an interactive graphical visualization tool.

DynaCORE — A Dynamically Reconfigurable Coprocessor Architecture for Network Processors

Network processors are special purpose processors, tailored to the needs of packet processing in internet routers. Network processors are, in general, freely programmable devices. However, their performance in payload processing relies on specific tasks to be accelerated by fixed purpose coprocessors which are integrated into the device. As a solution to overcome the restrictions of flexibility, a dynamically adaptable coprocessor based on dynamically and partially reconfigurable logic (DynaCORE) is proposed.

A comparison of feature descriptors for visual SLAM

Feature detection and feature description plays an important part in Visual Simultaneous Localization and Mapping (VSLAM). Visual features are commonly used to efficiently estimate the motion of the camera (visual odometry) and link the current image to previously visited parts of the environment (place recognition, loop closure). Gradient histogram-based feature descriptors, like SIFT and SURF, are frequently used for this task. Recently introduced binary descriptors, as BRIEF or BRISK, claim to offer similar capabilities at lower computational cost. In this paper, we will compare the most popular feature descriptors in a typical graph-based VSLAM algorithm using two publicly available datasets to determine the impact of the choice for feature descriptor in terms of accuracy and speed in a realistic scenario.

Communication Architectures for Dynamically Reconfigurable FPGA Designs

This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

An adaptive system-on-chip for network applications

This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. The coprocessor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns. An embedded general-purpose processor core within the coprocessor runs software which manages the configurations of the device. With reference to a prototypical implementation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues. Topics include the integration of PowerPC processor cores into the configurable logic as well as the mode of operation of the network-on-chip

Artificial Immune System Based Robot Anomaly Detection Engine for Fault Tolerant Robots

Robot anomaly detection method described in this paper uses an approach inspired by an immune system for detecting failures within autonomous robot system. The concept is based on self-nonself discrimination and clonal selection principles found within the natural immune system. The approach applies principles of fuzzy logic for representing and processing the information within the artificial immune system. Throughout the paper we explain the working principle of RADE (Robot Anomaly Detection Engine) approach and we show its practical effectiveness through several experimental test cases.

Reconfiguration and Checkpointing in Massively Parallel Systems

Despite the improvements in hardware design massively parallel systems lack on dependability due to the huge amount of components these systems consist of. One possibility to introduce fault-tolerance into such systems is backward error recovery where failed modules can be replaced by spares. The ESPRIT Project 6731 “A Practical Approach to Fault-Tolerant Massively Parallel Systems” follows such an approach and covers the aspects of error detection, diagnosis, checkpointing and reconfiguration. Target systems are multi-computers consisting of grid-wise connected modules using message passing. A first implementation will be made for the Parsytec GCel under PARIX. This paper focuses on recovery by reconfiguration and checkpointing. The project is based on switching in spares and routing around failed components via virtual links (interval routing). For the recovery a user-driven as well as a user-transparent approach are provided based on the new recovery-line-manager.

ORCA – towards an organic robotic control architecture

We are working on a modular and self-organizing component based software architecture for autonomous mobile robots. To reach a certain degree of fault-tolerance without analyzing all kinds of possible error conditions, “Organic Components” will be added to the system to detect recognize variations from a defined “normal state” and then try to find counter measures. Once an action is identified to help in certain situations, the component will store that information and use it if a similar situation is reached later. The system will be self-optimizing and self-healing. We started to evaluate adaptive filters as one possible implementation for components detecting deviations from the normal system state.

Experiences with a FPGA-based Reed/Solomon-encoding coprocessor

In this paper we present an implementation of a Reed/Solomon (R/S)-coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure-tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computational bandwidth, latency, and the hardware-software interaction. For comparison, software-based R/S-encoding implementations are presented and evaluated as well. The two variants of the FPGA-based coprocessors are compared to each other with respect to their fitting to a distributed storage application.