Ernst Hendrik August Granneman

H− Formation in proton-metal collisions

Abstract Negative hydrogen ion formation is studied by scattering protons from a cesiated tungsten (110) surface. The primary energy ranges from 50 to 400 eV. The angle of incidence is 70° with respect to the surface normal. A maximum conversion efficiency H − (H − + H 0 ) of 67% is measured. The measurements can be described in terms of the probability model. The perturbation of the H − ion by the metal is described within first order perturbation theory. A reasonable agreement between theory and experiment is obtained.

NiSi contact formation - process integration advantages with partial Ni conversion

Investigations for next generation contacts of silicon and SiGe devices show that a 2-step nickel salicidation process is favorable over a single step NiSi and over CoSi2 in every respect and can be introduced easily in existing and advanced not fully depleted CMOS flows once the post silicidation thermal treatments can be kept below 700degC. Partial conversion for the deposited Ni layer to Ni2 Si in a first RTP1 step at temperatures as low as 250degC avoids the reverse linewidth effect and enables superior uniformities over complete conversion. A second RTP2 step at typically 450degC is used to form low resistivity NiSi with less silicon consumption and lower contact resistivities than todays CoSi2 contacts. Challenging integration issue are peripheral leakage currents, that are likely to be related to undesired low temperature pyramidal NiSi2 formation and spiking

LPCVD of aluminium in a batch-type load-locked multi-chamber processing system

A reliable aluminium CVD technique for the filling of submicron contacts and vias providing good step coverage has been developed in a load-locked, batch-type, multichamber system. Because of the low resistivity of aluminium the subsequent metallization layer can be realized in the same process sequence. The Al CVD system configured consists of a reactor module, an I/O port, a bake-out annex activation module, a sputter deposition module, and an etch module, all grouped around an evacuated central wafer handling system which transfers wafers, on a single-wafer basis, in a vacuum of 2*10/sup -5/ Pa. The sputter deposition module provides the option to either deposit a sputtered diffusion barrier prior to the CVD film or to cap the CVD film with a Cu-doped sputtered Al layer to further enhance electromigration resistance. For a film thickness of 1 mu m, reflectivities of 55+or-5% are achieved at uniformities of +or-5%. Films exhibit resistivities of 2.8+or-0.2 mu Omega -cm and show good adhesion to most of the commonly used substrates. With a load of 30 wafers for each Al batch reactor, a throughput of 40 wafers per hour can be realized when two Al reactor modules are configured in one system.<<ETX>>

NiPt silicide agglomeration accompanied by stress relaxation in NiSi(010) ∥ Si(001) grains

Pt-doped Ni (NiPt) silicide agglomeration in terms of NiSi crystal orientation, Pt segregation at the NiSi/Si interface, and residual stress is studied for the first time. In the annealing of Ni monosilicide (NiSi), the growth of NiSi grains whose NiSi b-axes are aligned normal to Si(001) [NiSi(010) ∥ Si(001)] with increasing Pt segregation at the NiSi/Si interface owing to a high annealing temperature was observed. The residual stress in NiSi(010) ∥ Si(001) grains also increases with increasing annealing temperature. Furthermore, the recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress continues through additional annealing after NiSi formation. After the annealing of NiSi(010) ∥ Si(001) grains with their strain at approximately 2%, the start of NiPt silicide agglomerates accompanied by stress relaxation was observed. This preferential recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress is considered to enhance the NiPt silicide agglomeration.

Pattern-Dependent Heating of 3D Structures

Spike anneals based on radiation and conduction heating are carried out on silicon wafers with 12xl2mm2 patterned areas; these areas are covered with trenches with varying dimensions, thermally isolated from each other by large unpatterned silicon areas. The width of the trenches varies from 150-4500nm; the depths are 400 and 800nm. It is found that lamp-based heating with heatrup rates varying from 50-180degC/s results in temperature gradients of 10-45degC. In case of conduction heating in the conduction-based system (Levitor) no pattern-dependent temperature gradients are observed. A theoretical model was made such as to calculate the temperature gradient generated by the radiation heating process. In case of wide trenches, this model appears to predict the observed gradients reasonably well. However, in case of trenches < 450nm, the model overestimates the experimentally observed gradients.

Cluster-Tool Integrated HF Vapor Etching for Native Oxide Free Processing

Three regimes of HF-H 2 O vapor etching of oxide can be distinguished, viz. a gas phase, an adsorption and a condensation regime with gas phase etching behaving distinctily different in terms of etch rate and surface passivation properties. Integration of a vapor etch process in a vacuum-controlled, leak-tight cluster tool equipped with vertical reactor LPCVD and oxidation modules offers important thin film interface engineering capabilities; significant process control improvement is achievable in critical device technologies, such as formation of poly-contacts, poly-emitters and NO capacitors.

Process control improvements realized in a vertical reactor cluster tool

Advance cell structures present in high-density memories and logic devices require high quality, ultra thin dielectric and conductor films. By controlling the interface properties of such films, remarkable process control enhancements of manufacturing proven, vertical LPCVD and oxidation processes are realized. To this end, an HF/H2O vapor etch reactor is integrated in a vacuum cluster tool comprising vertical reactors for the various LPCVD and oxidation processes. Data of process control improvement are provided for polysilicon emitters, polysilicon contacts, polysilicon gates, and NO capacitors. Finally, the cost of ownership of cluster tool use is compared with that of stand-along equipment.

3D Pattern Effects in RTA Radiative vs Conductive Heating

Most studies on emissivity effects present during fast radiative heating of wafers generally focus on variation of the optical properties of the substrate across the wafer, within die, etc. This is usually well described by considering the differences in emissivity of the films or patterns that are present on the wafer. However, the absorption of radiation also varies when areas with different topography are present on the wafer and/or die. In the latter case, the effective emissivity varies between areas with different topographies, even though the deposited films are identical everywhere. This is because structures with large aspect ratios have a tendency to absorb radiation more efficiently than structures with less pronounced topographies, see fig. 1.

Conduction Heating in RTP Fast, and Pattern-Independent

Various types of conduction-based RTP systems are discussed. It is shown that simple hot plate systems suffer from severe bow of the wafer, when placed directly on the susceptor. This results in non-uniform heating. A solution is to place the wafer on pins; however, this considerably reduces the heat-up rate. An effective way to heat wafers through conduction fast and wellcontrolled is by placing it in a so-called gas bearing, an arrangement in which the wafer floats in between two hot blocks, at a well-controlled, small distance from both blocks. The heat-up rate in this so-called Levitor system is very high (~900°C/s) and uniform. It is demonstrated that this conduction-based system does not suffer from non-uniformities caused by variations in emissivity and/or pattern density across-wafer or within-die. In a direct comparison on pattern-dependent heating effects, substrates with trenches with varying dimensions are spike-annealed in a state-ofthe- art lamp system and in the Levitor. It was shown that temperature non-uniformities in the lampbased and the conduction-based systems are > 40°C and < 1°C, respectively. The conclusion is that the Levitor provides emissivity and pattern-independent heating.

Quantification of Si3N4 LPCVD inhibition on oxide surfaces

Abstract Si3N4 films were produced in an integrated vacuum processing system with separate modules for HF vapour etching, silicon thermal oxidation and LPCVD of Si3N4. It appears that the initial nucleation rate of the nitride growth depends strongly on the substrate surface. Si3N4 nucleates immediately on HF-vapour etched and thus oxide-free silicon, whereas on silicon oxide an appreciable retardation of growth takes place, which depends on the conditioning of the oxide prior to deposition. Conversion of the (O)N film into (O)NO, the dielectrics of choice in advanced memory capacitors, reveals that the degree of resistance of the nitride film against wet oxidation (“punch-through”) is directly related to the growth inhibition time and hence to the film micro-roughness. Details are presented on the relation between wafer pre-treatment, nitride process conditions, growth inhibition timw and the ultimate wet-oxidation resistance of the nitride film.