Essaid Bensoudane

StepNP: a system-level exploration platform for network processors

The fast-changing communications market requires high-performance yet flexible network-processing platforms. StepNP is an exploratory network processor simulation environment for exploring applications, multiprocessor network-processing architectures, and SoC tools. Supporting model interaction, instrumentation, and analysis, the platform lets R&D teams easily add new processors, coprocessors, and interconnects.

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

We describe the MultiFlex multi-processor SoC programming environment, with the focus on two programming models: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. The MultiFlex tools map these models onto the StepNP multi-processor SoC platform, while making use of hardware accelerators for message passing and task scheduling. We present the results of mapping an Internet traffic management application, running at 2.5 Gb/s.

Application of a multi-processor SoC platform to high-speed packet forwarding

In this paper, we explore the requirements of emerging complex SoCs and describe StepNP, an experimental flexible, multi-processor SoC platform targeted towards communications and networking applications. We present the results of mapping an internet protocol (IPv4) packet forwarding application, running at 2.5 Gb/s and 10 Gb/s. We demonstrate how the use of high-speed hardware-assisted messaging and dynamic task allocation in the StepNP platform allows us to achieve very high processor utilization rates (up to 97%) in spite of the presence of high network-on-chip and memory access latencies. The inter-processor communication overhead is kept very low, representing only 9% of instructions.

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures

This paper introduces an application mapping methodology and case study for multiprocessor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, and then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. The key contribution of this work is a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption. The methodology has been applied to the co-exploration of an industrial case study: an MPEG4 VGA realtime encoder

A 7.5Gb/s transmitter with self-adaptive FIR

This paper presents a transmitter FIR filter and a coefficient adaptation method based on exploration of the receive eye at the far end receiver. This method does not require backchannel or coding overhead and does not involve any proprietary functionality in the far-end SerDes. The transmitter FIR and the proposed adaptation method were proven in a CMOS 65 n SerDes over a variety of copper media for data-rates up to 9.4 Gbps.

Network processing challenges and an experimental NPU platform [network processor unit]

The fast-changing communications market requires high-performance yet flexible network-processing platforms. StepNP/spl trade/ is an exploratory network processor simulation environment for exploring router applications, multiprocessor network-processing architectures, and SoC tools. Supporting model interaction, instrumentation, and analysis, the platform lets R&D teams easily add new processors, coprocessors, and interconnects.

System-level design of continuous/discrete-time heterogeneous systems applied to high-speed serial link

Many existing and future systems are and will be composed by several significantly heterogeneous modules, including both continuous and discrete components. This broad class of systems includes analog/mixed-signal systems composed of RF, analog, analog-to-digital and digital-to-analog conversions, and recently, a large number of mixed-signal chips where at least part of the chip design needs to measure signals with high precision. Comparing with the digital circuits, these chips have very different design and process technology demands. This paper presents an approach for system-level design of continuous/discrete systems, focusing the role of the bottom-up iterations. The approach is applied to the design of a high-speed serial link.

Two-level tiling for MPSoC architecture

Multiprocessor systems-on-a-chip (MPSoCs architectures) have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of several level of memory hierarchy. Usually tiling is applied to one loop nest; in this paper we apply simultaneously loop fusion with two-level tiling to several loop nests in the context of a MPSoC architecture. The two level-tiling allows the simultaneous optimization of caches and registers. To optimize the memory space used by temporary arrays, buffers and registers are used as a replacement. The experiments show that these techniques yield a significant reduction in the number of data cache misses and in processing time.