Etienne Hirt

AMON: a wearable medical computer for high risk patients

We present a wrist worn medical monitoring computer designed to free high risk patient from the constraints of stationary monitoring equipment. The system combines complex medical monitoring, data analysis and communication capabilities in a truly wearable watch-like form. The paper summarizes the functionality, architecture and implementation of the system.

Area I/O's potential for future processor systems

Bandwidth, latency, system speed, and, of course, the size of future microprocessor systems all highly depend on interconnection technologies. Interconnection will become the key performance bottleneck as semiconductor technology improvements continue to reduce feature size. In this article, we describe the use of on-chip area I/O for future microprocessor systems on the basis of a case study we made of an Intel Pentium system. Area I/O is simply a method of locating I/Os over the entire chip instead of just the periphery. We show that system designers can achieve significant performance gains with area I/O and size reductions at both the system and chip levels. We also explain how area I/O in conjunction with high-density interconnects leads to a new package and chip partitioning concept.

Virtual prototyping for high density packaging systems

Very early in an electronic design cycle the physical buildup of a system, such as bonding method, substrate technology, and number of layers, needs to be chosen before any layout is performed. But when developing high density systems, a huge number of technology choices are available, each having impact on various aspects of the system performance. This paper describes virtual prototyping as a method for systematically analyzing and choosing the suitable buildups and selecting one of them in a cost-performance analysis for implementation and layout. Unlike former design advisors, our method analyzes several possibilities in parallel, allowing for a better design space exploration. The framework is implemented in the Java based tool JavaCAD, JavaCAD manages the different buildups and provides a size/layer count estimation for all first level interconnect/packages on various substrate technologies. It calculates the component footprints, analyzes the routing with as few data as available and allows cost estimation of all feasible buildups. The benefits of our approach are illustrated in the design of a 9:4 satellite switch operating at 2.4 GHz.

DfT techniques for first-time right MCMs-exemplified by a Pentium MCM system

The controllability and observability aspects of MCM test must be considered at a very early design stage, which is widely known as design for testability (DfT). In order to demonstrate the advantages of DfT strategies for complex MCM designs, the Electronics Laboratory of the Swiss Federal Institute of Technology in Zurich has developed a thin film MCM-D which incorporates a Pentium processor with associated chip set and memory (512 kbyte of second level cache). This means that different test structures (and underlying DfT philosophies) of commercially available chips, like BIST, boundary-scan and NAND trees, had to be combined with chips for which none of these structures are available. The challenge for such a design is to develop the most effective and, especially, cost-effective DfT strategy that allows testing of an MCM to the same level as packaged components, as well as providing quick and accurate fault localization to allow rework in the manufacturing process. The paper briefly introduces the demonstrator MCM, and gives an overview of the different structures utilized. The main focus of the paper is, however, placed on the implementation of the DfT technologies actually used in the MCM design by identifying and analyzing the different options. This was done using a consequent top-down methodology to manage the complexity of this processor based MCM. The paper then presents, discusses and evaluates real test results obtained on the Electronic Laboratorys industrial HP83000 F330t test system and draws conclusions about the effectiveness of the approach.