Ettore Messina

A fully integrated 24GHz UWB radar sensor for automotive applications

Radar-based advanced safety systems are crucial to reduce road accidents caused by driver inattention. An actual and pervasive adoption of radar technology requires the development of low-cost Silicon-integrated sensors, including microwave, analog, and digital blocks on a single chip, able to replace existing discrete electronics based on compound semiconductors. Indeed, the considerable advantage of Silicon lies in its natural capability for integration that will enable a higher level of complexity in such sensors. Recent Silicon implementations [1, 2] have proved the maturity of both high-speed bipolar and submicron CMOS processes for multi-GHz applications, such as 24GHz automotive short-range radar (SRR). However, the implementation of a complete radar sensor on a single chip is still very challenging and involves a proper radar architecture (i.e., continuous-wave or pulsed radar), efficient detection methodology, a robust radio front-end structure and customized local DSP. In this scenario, UWB sensors based on analog correlation RX represent an attractive solution for a cost-effective automotive SRR [3].

Serial block processing for multi-code WCDMA frequency domain equalization

This paper presents an efficient implementation of a frequency domain linear equalizer for WCDMA systems. A significant complexity reduction with respect to traditional equalizers can be achieved by means of frequency domain block processing. After deriving the analytical formulation of the equalizer coefficients, it is shown that the performance of the frequency domain equalizer (FDE) is substantially equivalent to that of the classical time domain equalizer (TDE) over a wide range of operating conditions so that no penalty has to be paid for the complexity reduction. Starting from a pure parallel implementation of the FDE, it is shown that block processing for multi-code downlink WCDMA can be conveniently performed in a serial fashion, through properly reusing small processing elements while exploiting the pipeline in order to reduce the subsequent latency overhead.

Automatic Gain Control Loop Based on Threshold Crossing Rate Measurement

In a mobile telecommunication system the received signal envelope has a very large dynamic range. A gain control is then required to adjust the signal amplitude at the input of the Analog to Digital Converter, ADC. The Automatic Gain Control, AGC, must control such amplitude to avoid (or limit) ADC saturation and, at the same time, to ensure an efficient usage of its dynamic range. In the state of art approach, the AGC loop adjustment is based on the measurement of the received signal power. This measurement can be made directly from the RF unit or after the ADC. In this contribution, we describe an approach based on indirect power measurement with low complexity circuitry. Shortly, this method measures the signal probability of exceeding a properly defined threshold, allowing power estimate.

ASIP Architecture for Multi-Standard Wireless Terminals

This paper presents the block processing engine (BPE), an application specific instruction-set processor (ASIP) explicitly designed for the implementation of multi-standard wireless terminals. Thanks to a high level of parallelism and a consistent use of pipeline, the BPE architecture fully satisfies stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation, the physical synthesis for the CMOS 90nm STM technology and the FPGA prototyping on the ARM Versatile platform of a dual-standard frequency domain equalizer (FDE) supporting the 3GPP HSDPA and the IEEE 802.11a standards

On the Acquisition Ambiguity for Galileo BOC(n,n) Modulated Signals

Binary offset carrier, BOC, modulated signals are at the moment candidates both for new civil (free) signal in GPS update and for part of the European Global Navigation Satellite System (GNSS) Galileo. They present better multipath mitigation and, potentially, better tracking characteristic but they have a multiple peak autocorrelation function. These secondary peaks could introduce problems both in acquisition and tracking stage, when usual approaches are employed at the receiver. Several possible strategies for mitigating lock ambiguities in acquisition and tracking, related to secondary peaks, have been presented in the past for BOC modulated signals. In this contribution we focus our attention on BOC(n,n) modulated signal, and analyze in detail the acquisition ambiguity problem versus the acquisition approach. We also present performance comparison (detection probability, probability of lock on secondary auto-correlation peaks) considering several test variables for the acquisition process. All the results are presented for the L1 Galileo signal format.

Block processing engine for high-throughput wireless communications

This paper presents the block processing engine (BPE), a programmable architecture specifically suited for high-throughput wireless communications. Thanks to a high degree of parallelism and a consistent use of pipelined processing, the BPE can satisfy the stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation of a dual standard frequency domain equalizer supporting 3GPP HSDPA and IEEE 802.11a.