Eunkyeom Kim

Thermal boundary resistance at Ge2Sb2Te5/ZnS:SiO2 interface

The thermal conductivity of sputtered amorphous-Ge2Sb2Te5u200a(a-GST)/ZnS:SiO2 and crystalline-Ge2Sb2Te5u200a(c-GST)/ZnS:SiO2 multilayer films has been measured in the temperature range between 50 and 300 K using the 3ω method. The conductivity data in the direction of the cross plane of the films showed lower values than the series conductance of the constituent layers, which was calculated from the thermal conductivity of thick a-GST, c-GST, and ZnS:SiO2 films measured independently. From the reduction in the multilayer thermal conductivity, the thermal boundary resistance at the interface between GST and ZnS:SiO2 films was calculated. The boundary resistance in the c-GST multilayer was lower than that for the a-GST case in the whole measured temperature region.

SiNx charge-trap nonvolatile memory based on ZnO thin-film transistors

We have demonstrated the fabrication and application of a nonvolatile thin-film transistor memory with SiNx charge traps using a ZnO thin film as the active channel layer. The thin film of ZnO was deposited using an atomic-layer deposition process and was subsequently post-annealed in an O2-filled atmosphere. X-ray diffraction and x-ray photoemission results indicated that the O2 annealing process was effective for the crystallinity and stoichiometry of the ZnO films. A saturation field-effect mobility of 6 cm2/Vs, on/off ratio of ≈105, subthreshold slope of 0.7 V/decade, and threshold voltage of −5 V were obtained in transistor operations. Threshold-voltage shift measurements performed for various stress voltages and time durations revealed that these devices had a large memory window of 5.4 V and a long retention time (>10 years) in nonvolatile memory operations.

Dual dielectric tunnel barrier in silicon-rich silicon nitride charge-trap nonvolatile memory

We investigated a tunnel barrier with dual (SiO2 and SiNx) dielectric layers in charge-trap nonvolatile memories to improve the program/erase speed and charge retention characteristics. Threshold voltage shift measurements performed for various stress voltages and time durations revealed that these devices had a large memory window (2–6 V) and long retention time (>10u2002years). With a decrease in the SiO2 layer thickness, the program speed increased but the erase speed decreased. The change in the program/erase speed and charge retention characteristics with the relative thickness ratio could be attributed to the asymmetric shape of the tunnel barrier. The tunneling currents were explained on the basis of Fowler–Nordheim tunneling and Frenkel–Poole emission in the asymmetric tunnel barrier.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

Resistive switching behaviors of the ZnO/SiO x /ZnO tri-layer for nonvolatile memory devices

Bipolar resistive switching effects were investigated for nonvolatile memory applications in a ZnO/SiOx/ZnO structure. ZnO thin films were grown by radio frequency magnetron sputtering at room temperature. And SiOx films were grown by plasma enhanced chemical vapor deposition (PECVD) at 200 °C. The resistance ratios of high/low resistance state were in the range of about 1 order. The resistive random access memory with this structure will show a great promise for high density memory device.