Eva M. Ortigosa

Event-driven simulation scheme for spiking neural networks using lookup tables to characterize neuronal dynamics

Nearly all neuronal information processing and interneuronal communication in the brain involves action potentials, or spikes, which drive the short-term synaptic dynamics of neurons, but also their long-term dynamics, via synaptic plasticity. In many brain structures, action potential activity is considered to be sparse. This sparseness of activity has been exploited to reduce the computational cost of large-scale network simulations, through the development of event-driven simulation schemes. However, existing event-driven simulations schemes use extremely simplified neuronal models. Here, we implement and evaluate critically an event-driven algorithm (ED-LUT) that uses precalculated look-up tables to characterize synaptic and neuronal dynamics. This approach enables the use of more complex (and realistic) neuronal models or data in representing the neurons, while retaining the advantage of high-speed simulation. We demonstrate the methods application for neurons containing exponential synaptic conductances, thereby implementing shunting inhibition, a phenomenon that is critical to cellular computation. We also introduce an improved two-stage event-queue algorithm, which allows the simulations to scale efficiently to highly connected networks with arbitrary propagation delays. Finally, the scheme readily accommodates implementation of synaptic plasticity mechanisms that depend on spike timing, enabling future simulations to explore issues of long-term learning and adaptation in large-scale networks.

Real-time computing platform for spiking neurons (RT-spike)

A computing platform is described for simulating arbitrary networks of spiking neurons in real time. A hybrid computing scheme is adopted that uses both software and hardware components to manage the tradeoff between flexibility and computational power; the neuron model is implemented in hardware and the network model and the learning are implemented in software. The incremental transition of the software components into hardware is supported. We focus on a spike response model (SRM) for a neuron where the synapses are modeled as input-driven conductances. The temporal dynamics of the synaptic integration process are modeled with a synaptic time constant that results in a gradual injection of charge. This type of model is computationally expensive and is not easily amenable to existing software-based event-driven approaches. As an alternative we have designed an efficient time-based computing architecture in hardware, where the different stages of the neuron model are processed in parallel. Further improvements occur by computing multiple neurons in parallel using multiple processing units. This design is tested using reconfigurable hardware and its scalability and performance evaluated. Our overall goal is to investigate biologically realistic models for the real-time control of robots operating within closed action-perception loops, and so we evaluate the performance of the system on simulating a model of the cerebellum where the emulation of the temporal dynamics of the synaptic integration process is important.

Hardware description of multi-layer perceptrons with different abstraction levels

Abstract This paper presents different hardware implementations of a multi-layer perceptron (MLP) for speech recognition. When defining the designs, we have used two different abstraction levels: a register transfer level and a higher algorithmic-like level. The implementations have been developed and tested into reconfigurable hardware (FPGA) for embedded systems. We also present a comparative study of the costs for the two considered approaches with regards to the silicon area, speed and required computational resources. The research is completed with the study of different implementation versions with diverse degrees of parallelism. The final aim is the comparison of the methodologies applied in the two abstraction levels for designing hardware MLP’s or similar computational structures.

Parallel scheduling of the PCG method for banded matrices rising from FDM/FEM

An implicit time-linearized finite difference discretization of partial differential equations on regular/structured meshes results in an n-diagonal block system of algebraic equations, which is usually solved by means of the Preconditioned Conjugate Gradient (PCG) method. In this paper, an analysis of the parallel implementation of this method on several computer architectures and for several programming paradigms is presented. For three-dimensional regular/structured meshes, a new implementation of the PCG method with Jacobi preconditioner is proposed. For the computer architectures and number of processors employed in this study, it has been found that this implementation is more efficient than the standard one, and can be applied to narrow-band matrices and other preconditioners, such as, for example, polynomial ones.

FPGA Implementation of Multi-layer Perceptrons for Speech Recognition

In this work we present different hardware implementations of a multi-layer perceptron for speech recognition. The designs have been defined using two different abstraction levels: register transfer level (VHDL) and a higher algorithmic-like level (Handel-C). The implementations have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. A study of the two considered approaches costs (silicon area), speed and required computational resources is presented.

Hardware event-driven simulation engine for spiking neural networks

The efficient simulation of spiking neural networks (SNN) remains an open challenge. Current SNN computing engines are still far away from simulating systems of millions of neurons efficiently. This contribution describes a computing scheme that takes full advantage of the massive parallel processing resources available at FPGA devices. The computing engine adopts an event-driven simulation scheme and an efficient next-event-to-go searching method to achieve high performance. We have designed a pipelined datapath, in order to compute several events in parallel avoiding idle computing resources. The system is able to compute approximately 2.5 million spikes per second. The whole computing machine is composed only of an FPGA device and five external memory SRAM chips. Therefore, the presented approach is of high interest for simulation experiments that require embedded simulation engines (for instance, in robotic experiments with autonomous agents).

Bio-Inspired Motion Detection for a Blind Spot Overtaking Monitor

The rear-view mirror is unhelpful when an overtaking car is in the blind quadrants (blind spot). In this contribution we describe the software implementation of an algorithm to monitor vehicle overtaking processes. This algorithm detects the vehicle to the rear, and discriminates whether it is approaching or not, and if approaching, it alerts us of its presence. The proposed system is based on the Reichardt correlator model [1]. The approach presented uses the saliency of motion features in a competition scheme to filter noise patterns. In this way features corresponding to rigid body motion self-emerge from the background. Real overtaking sequences have been to develop this monitoring system.

Swad: Web System for Education Support

This chapter presents a platform for supporting education tasks; we call it SWAD (in Spanish, it stands for Web-System for Education Support). This platform has been gradually developed during the last 7 years and is currently used at the University of Granada in more than 578 different subjects of different degrees. We describe here the various web services provided by the platform for students and educators, such as electronic index card, class photograph, document downloading, student self-assessment through multiple-choice exam, online checking of grades, internal web mail, discussion forums and electronic blackboard. The chapter also gives details about its implementation and provides evaluation statistics about its use and users’ opinions after testing the platform.

Post-synaptic Time-dependent Conductances in Spiking Neurons: FPGA Implementation of a Flexible Cell Model

This work presents a flexible reconfigurable approach to a bioinspired spiking neuron. The main objective of this contribution is to evaluate the silicon cost of the implementation of lime-dependent conductances in spiking neurons. The design presented here has been defined using a high level Hardware Description Language (HDL). This facilitates the extraction of simulation results, and the easy change of the circuit. The paper discusses how different aspects of lime-dependent conductances can be particularized in the circuit, and Iheir hardware requirements.

Motion-Driven Segmentation by Competitive Neural Processing

Bio-inspired energy models compute motion along the lines suggested by the neurophysiological studies of V1 and MT areas in both monkeys and humans: neural populations extract the structure of motion from local competition among MT-like cells. We describe here a neural structure that works as a dynamic filter above this MT layer for image segmentation and takes advantage of neural population coding in the cortical processing areas. We apply the model to the real-life case of an automatic watch-out system for car-overtaking situations seen from the rear-view mirror. The ego-motion of the host car induces a global motion pattern whereas an overtaking vehicle produces a pattern that contrasts highly with this global ego-motion field. We describe how a simple, competitive, neural processing scheme can take full advantage of this motion structure for segmenting overtaking-cars