Evan Heller

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx-cladded Si or GeOx-cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx-cladded Si and GeOx-cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (ID–VG) shows four-state behavior with two intermediate states between the conventional ON and OFF states.

Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: device and circuit modeling

In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 /spl mu/m channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.

Mixed-level optical simulations of light-emitting diodes based on a combination of rigorous electromagnetic solvers and Monte Carlo ray-tracing methods

Abstract. Over the last two decades, extensive research has been done to improve light-emitting diodes (LEDs) designs. Increasingly complex designs have necessitated the use of computational simulations which have provided numerous insights for improving LED performance. Depending upon the focus of the design and the scale of the problem, simulations are carried out using rigorous electromagnetic (EM) wave optics-based techniques, such as finite-difference time-domain and rigorous coupled wave analysis, or through ray optics-based techniques such as Monte Carlo ray-tracing (RT). The former are typically used for modeling nanostructures on the LED die, and the latter for modeling encapsulating structures, die placement, back-reflection, and phosphor downconversion. This paper presents the use of a mixed-level simulation approach that unifies the use of EM wave-level and ray-level tools. This approach uses rigorous EM wave-based tools to characterize the nanostructured die and generates both a bidirectional scattering distribution function and a far-field angular intensity distribution. These characteristics are then incorporated into the RT simulator to obtain the overall performance. Such a mixed-level approach allows for comprehensive modeling of the optical characteristic of LEDs, including polarization effects, and can potentially lead to a more accurate performance than that from individual modeling tools alone.

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic

This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.

Optical simulations of organic light-emitting diodes through a combination of rigorous electromagnetic solvers and Monte Carlo ray-tracing methods

Over the last two decades there has been extensive research done to improve the design of Organic Light Emitting Diodes (OLEDs) so as to enhance light extraction efficiency, improve beam shaping, and allow color tuning through techniques such as the use of patterned substrates, photonic crystal (PCs) gratings, back reflectors, surface texture, and phosphor down-conversion. Computational simulation has been an important tool for examining these increasingly complex designs. It has provided insights for improving OLED performance as a result of its ability to explore limitations, predict solutions, and demonstrate theoretical results. Depending upon the focus of the design and scale of the problem, simulations are carried out using rigorous electromagnetic (EM) wave optics based techniques, such as finite-difference time-domain (FDTD) and rigorous coupled wave analysis (RCWA), or through ray optics based technique such as Monte Carlo ray-tracing. The former are typically used for modeling nanostructures on the OLED die, and the latter for modeling encapsulating structures, die placement, back-reflection, and phosphor down-conversion. This paper presents the use of a mixed-level simulation approach which unifies the use of EM wave-level and ray-level tools. This approach uses rigorous EM wave based tools to characterize the nanostructured die and generate both a Bidirectional Scattering Distribution function (BSDF) and a far-field angular intensity distribution. These characteristics are then incorporated into the ray-tracing simulator to obtain the overall performance. Such mixed-level approach allows for comprehensive modeling of the optical characteristic of OLEDs and can potentially lead to more accurate performance than that from individual modeling tools alone.

Accounting for coherent effects in the ray-tracing of light-emitting diodes with interface gratings via mixed-level simulation

Abstract. Ray-tracing (RT) has long been the workhorse technique for analyzing light-emitting diode (LED) dies and packages and has led to significant improvements in extraction efficiency and beam shaping. However, to achieve further enhancements, nano-/microscale features such as patterned substrates and surface textures have been explored. The coherent effects arising from these near/subwavelength features are difficult to include in the RT of the packaged device. We show that under certain conditions these effects can have a significant impact on LED performance, especially if back-reflectors are present. Furthermore, we demonstrate that coherence must be accounted for even in structures that would otherwise be considered as having relatively large feature sizes, such as gratings with periods many times the wavelength. We present comparisons between the optical responses of prototypical periodically patterned substrates modeled with RT alone and with a mixed-level approach that combines RT and rigorous electromagnetic simulation, such as rigorous coupled wave analysis and finite-difference time-domain. Several examples with varying lateral periods are computed with both methods. It is shown that these results may differ, and that these differences can be significant if back reflection is present. We conclude that a mixed-level approach is an efficient and accurate method to model light extraction in modern LEDs.

Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn0.95Mg0.05S as the gate insulator is presented in this paper, showing three output states which can be used in multibit logic applications. The spatial wavefunction switching effect in this transistor has been investigated, and modeling simulations have shown supporting evidence that additional output states can be achieved in one transistor.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells

This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiOx-cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in ID–VG characteristics is presented after the ‘Write’ cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II–VI layer as the gate insulator.

Multi-Bit Quantum Dot Nonvolatile Memory (QDNVM) Using Cladded Germanium and Silicon Quantum Dots

In this paper, we are experimentally demonstrating the multi-bit storage of a nonvolatile memory device with cladded quantum dots as the floating gate. These quantum dot nonvolatile memory (QDNVM) devices were fabricated by using standard complementary metal-oxide-semiconductor (CMOS) process. The quantum dots in the floating gate region assembled using site-specific selfassembly (SSA) technique. Quantum mechanical simulations of this device structure are also presented. The experimental results show that the voltage separation between the bits was 0.15V and the voltage pulses required to write these bits were 11.7V and 30V. These devices demonstrated the larger write voltage separation between the bits.