Ezz I. El-Masry

A Novel CMOS OTA Based on Body-Driven MOSFETs and its Applications in OTA-C Filters

The operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Traditional OTAs suffer linearity reduction as a result of the MOSFET scaling trend. In this paper, a body-driven (BD) CMOS triode-based fully balanced OTA is proposed to achieve low distortion and linear frequency tuning. In contrast to the gate-driven based OTAs (that have the tradeoff of input and tuning range), BD-based OTAs operate under a wide input range over a large tuning interval. Common-mode (CM) feedforward and CM feedback schemes have been developed so that the CM voltage varies only 7 mV over a tuning range of 1.2 V = Vtune = 1.58 V. Using the 0.18-mum N-well CMOS process, a third-order elliptic low-pass filter is implemented with the aid of the proposed OTA. The total harmonic distortion ( is -45 dB for 0.8-V peak-peak (Vpp) fully differential input signals. A dynamic range of 45 dB is obtained with the OTAs noise integrated over 1 MHz.

A 200 MHz steered current operational amplifier in 1.2-/spl mu/m CMOS technology

In this paper, we present the design of a CMOS current operational amplifier (COA). A design technique based on current steering is proposed to enhance the frequency capability of the amplifier and achieve higher bandwidth of operation. A complete COA was designed and fabricated using a 1.2-/spl mu/m CMOS technology, the COA occupies an area of 0.13 mm/sup 2/. Results from HSPICE simulations and measurements indicate an open-loop gain of 70 dB, a gain-bandwidth product exceeding 200 MHz, and a settling time of 5.1 ns. The amplifier operated under /spl plusmn/3 V DC voltage supplies, and the power dissipation is approximately 4.5 mW.

Design of current-mode ladder filters using coupled-biquads

A new design approach for current-mode (CM) filters is presented. The proposed method is based on simulating RLC ladder networks using coupled-biquad structures. The loop-and branch-currents are used as variables to generate transfer functions. These functions are realized by CM circuits implementing multiple output CMOS OTAs. The resulting CM structures use only grounded capacitors making them suitable for VLSI. To demonstrate the proposed approach, a low-pass and a band-pass ladder filter were designed and simulated using HSPICE.

A novel continuous-time current-mode differentiator and its applications

A novel continuous-time current-mode differentiator with a frequency range extending from DC to 100 MHz is presented. This circuit is constructed using a capacitively coupled current mirror. General first- and second-order circuits, using the differentiator, have also been introduced. To demonstrate how the proposed differentiator can be used to construct higher order filters, a sixth-order band-pass filter with a center frequency at 2.5 MHz and a 1 dB pass-band ripple has been realized and simulated. All simulations were performed using HSPICE for a 1.2 /spl mu/m CMOS process. The total power dissipation for the sixth-order filter is 23 mW from a single 3 V supply.

A novel low-voltage operational transconductance amplifier and its applications

A new CMOS realization of an operational transconductance amplifier is presented. It is based on the cross-coupled configuration and is biased by the common-mode voltage. The circuit has only two transistors between the supply line and ground which makes it suitable for low-voltage applications. Simulation results show that the circuit is highly linear and tunable over a wide range bias voltage. The circuit is used to realize 2/sup nd/ generation current conveyor (CCII) and differential current conveyor (DCC) that have excellent performance.

Distributed MOSFET high-pass filters

A method for the analysis of distributed MOSFET filters is presented. The effects of parasitic capacitances on distributed high-pass MOSFET filters are investigated. Three schemes of MOSFET configurations functioning as distributed high-pass filters are presented and analyzed to demonstrate the method and to illustrate the parasitic effects. The analyses are verified by SPICE simulation and the very high frequency numerical model of a MOSFET given by L.J. Pu and Y. Tsividis (1990). >

A novel double sampling technique for delta-sigma modulators

The double sampling technique is used to achieve twice the sampling frequency in sampled-data systems without extra requirements (e.g., clock rate, op-amp settling time, op-amp dc gain, etc.). In this paper, theoretical analyses of the effects of nonidealities (integrator leakage, path gain mismatch and non-uniform sampling) on the performance of double sampling delta-sigma modulators (/spl Delta//spl Sigma/Ms) are given. A novel double sampling technique for /spl Delta//spl Sigma/Ms which is insensitive to the path gain mismatch is also presented. This technique uses a bilinear integrator in the first stage, resulting in a first order shaping of the path gain mismatch error. Compared with a second-order single sampling /spl Delta//spl Sigma/M, this technique is able to achieve 15 dB improvement of S/N and 6 dB relaxation of op-amp dc gain.

Switched-current analysis program

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

CMOS front end RF amplifier with on-chip tuning

In this paper we present a CMOS front-end amplifier with on chip tuning circuitry. The design is targeted towards applications in wireless RF communications. In the design, integrated inductors are used to provide frequency tuning and impedance matching capabilities. Negative resistance is used to compensate for the losses in these inductors in order to achieve reasonable quality factors. Two amplifiers of the same topology were designed using a 1.5 /spl mu/m p-well process to operate at 900 MHz and 1.9 GHz. Simulation using HSPICE show that quality factors exceeding 20 are possible. The amplifiers provide gains of 23 dB and noise figures of approximately 5 dB.

Biquadratic high-pass and low-pass single-MOSFET filters

A novel method for analyzing distributed MOSFET filters is presented. The transfer functions of single-MOSFET high-pass and low-pass filters in biquadratic form are obtained using the method. The characteristic frequency and the Q-factor of the high-pass and low-pass filters are directly related to the standard electrical, geometrical, and process parameters of an MOS transistor. It is found that the characteristic frequency of the filter is around three times the intrinsic cutoff frequency of a MOS transistor. To obtain higher-order high-pass and low-pass filters with minimal number of transistors, cascade structures for single-MOSFET filters are proposed. It is shown that MOS transistors in a cascaded chain are required to have a certain channel width ratio to achieve impedance matching. A sixth-order filter can be realized using only three distributed MOS transistors.<<ETX>>