F. Belanger

The Hardware and Signal Processing Architecture of LabPET™, a Small Animal APD-Based Digital PET Scanner

The highly multiplexed analog processing front-end of current Positron Emission Tomography (PET) scanners yields high accuracy for timing but adds significant dead time and offers little flexibility for improvement. A new fully digital APD-based scanner architecture is proposed wherein nuclear pulses are sampled directly at the output of the Charge Sensitive Preamplifier (CSP) with one free-running ADC per channel. This approach offers the opportunity to explore new digital signal processing algorithms borrowed from other fields like command and control theory, as well as advanced heuristics such as neural networks. The analog front-end consists of a dedicated 0.18- mum, 16-channel CMOS charge sensitive preamplifier. Digitization is performed with off-the-shelf dual 8-bit analog-to-digital converters running at 45-MSPS. Digital processing is shared between a FPGA and a Digital Signal Processor (DSP), which can process the data from up to 64 parallel channels without dead time. The FPGA deals with the initial signal analysis for energy measurement and time stamping, while crystal identification is deferred to the DSP running computation-intensive recursive algorithms. The entire system is controlled serially through a Firewire link by a Graphic User Interface. The initial LabPETtrade implementation of the system is a dedicated small animal scanner holding up to 4608 APD channels at an averaged count rate of up to 10 000 events/s each.

System Architecture of the LabPET Small Animal PET Scanner

To address modern molecular imaging requirements, a digital positron emission tomography (PET) scanner for small animals has been developed at Universite de Sherbrooke. Based on individual readout of avalanche photodiodes (APD) coupled to LYSO/LGSO phoswich detectors, the scanner supports up to 4608 channels in a 16.2 cm diameter, 11.25 cm axial field of view with an isotropic ~ 1.2 mm FWHM intrinsic spatial resolution at the center of the field of view. Custom data acquisition boards preprocess and sample APD signals at 45 MHz and compute in real time crystal identification, energy and timing information of detected events at an average sustained rate of up to 1250 raw counts per second per mm2 (10 000 cps/channel). Real time digital signal analysis also filters out events outside the pre-selected energy window with crystal granularity to eliminate Compton events and electronic noise. Retained events are then merged into a single stream through a real-time sorting tree, at which end prompt and delayed coincidences are extracted. A single Firewire link handles both control and data transfers with a host computer. The LabPET features four data recording modes, giving the user the choice to retain data for research or to minimize file size for high coincidence count rate and imaging purposes. The electronic system also supports time synchronized data insertion for flags such as vital signs used in gated image reconstruction. Aside from data acquisition, hardware can generate live energy and discrimination spectra suitable for fast, automatic channel calibration.

Architecture of a dual-modality, high-resolution, fully digital positron emission tomography/computed tomography (PET/CT) scanner for small animal imaging

Contemporary positron emission tomography (PET) scanners are commonly implemented with very large scale integration analog front-end electronics to reduce power consumption, space, noise, and cost. Analog processing yields excellent results in dedicated applications, but offers little flexibility for sophisticated signal processing or for more accurate measurements with newer, fast scintillation crystals. Design goals of the new Sherbrooke PET/computed tomography (CT) scanner are: 1) to achieve 1 mm resolution in both emission (PET) and transmission (CT) imaging using the same detector channels; 2) to be able to count and discriminate individual X-ray photons in CT mode. These requirements can be better met by sampling the analog signal from each individual detector channel as early as possible, using off-the-shelf, 8-b, 100-MHz, high-speed analog-to-digital converters (ADC) and digital processing in field programmable gate arrays (FPGAs). The core of the processing units consists of Xilinx SpartanIIe that can hold up to 16 individual channels. The initial architecture is designed for 1024 channels, but modularity allows extending the system up to 10 K channels or more. This parallel architecture supports count rates in excess of a million hits/s/scintillator in CT mode and up to 100 K events/s/scintillator in PET mode, with a coincidence time window of less than 10 ns full-width at half-maximum.

The architecture of LabPET/spl trade/, a small animal APD-based digital PET scanner

The highly multiplexed, integrated analog processing front-end of current PET scanners yields high accuracy for timing and crystal identification, but also adds significant dead time and offers little flexibility for improvement. A new fully digital APD-based scanner architecture is proposed wherein nuclear pulses are sampled directly at the output of the charge sensitive preamplifier with one free-running ADC per channel. This approach offers the opportunity to explore new digital signal processing algorithms borrowed to command and control theory, as well as advanced heuristics such as neural networks. The analog front-end consists of a dedicated 0.18-mum, 16-channel CMOS charge sensitive preamplifier. Digitization is performed with off-the-shelf dual 8-bit 45-MHz analog-to-digital converters. Digital processing is concentrated in a dual processor FPGA and a digital signal processor (DSP), which can process the data from up to 64 parallel channels with no dead time. The FPGA deals with the initial signal analysis for energy measurement and time stamping, while crystal identification is deferred to the DSP running computation-intensive auto-regressive algorithms. The entire system is controlled serially through a Firewire link by a graphic user interface. The initial LabPETtrade implementation of the system is a dedicated small animal scanner holding up to 3072 APD channels at an averaged count rate of up to 10 000 events/s each

Real time digital signal processing implementation for an APD-based PET scanner with phoswich detectors

Recent progress in advanced digital signal processing provides an opportunity to expand the computation power required for real time extraction of event characteristics in APD-based positron emission tomography (PET) scanners. These developments are made possible by a highly parallel data acquisition (DAQ) system based on an integrated analog front-end and a high-speed fully digital signal processing section that directly samples the output of each preamplifier with a free-running, off-the-shelf, 45-MHz MAX1193 analog-to-digital converter that feeds the sampled data into a field programmable gate array VirtexII PRO from Xilinx. This FPGA features ~31,000 logic cells and 2 PowerPC processors, which allows up to 64 channels to be processed simultaneously. Each channel has its own digital signal processing chain including a trigger, a baseline restorer and a timestamp algorithm. Various timestamp algorithms have been tested so far, achieving a coincidence timing resolution of 3.2 ns FWHM for APD-LSO and 11.4 ns FWHM for APD-BGO detectors, respectively. Channels are then multiplexed into a TMS320C6414 DSP processor from Texas Instruments for crystal identification by an ARMAX recursive algorithm borrowed from identification and vector quantization theory. The system can sustain an event rate of 10 000 events/s/channel without electronic dead time

Crystal Identification Based on Recursive-Least-Squares and Least-Mean-Squares Auto-Regressive Models for Small Animal Pet

Most positron emission tomography (PET) scanners still partly rely on analog processing to sort out events from the PET detector front-end. Recent all-digital architectures enable the use of more complex algorithms to solve common problems in PET scanners, such as crystal identification and parallax error. Auto-regressive exogeneous variable (ARX) algorithms were shown to be among the most powerful methods of crystal identification by pulse shape discrimination (PSD) for parallax mitigation or resolution improvement with phoswich detectors. Although ARX algorithms achieve a nearly 100% discrimination accuracy even in a noisy environment, such methods are computationally expensive and can hardly be implemented in a real time digital PET system. A crystal identification method based on adaptive filter theory using an auto-regressive (AR) model is proposed to enable real time crystal identification in a noisy environment.

System Integration of the LabPET Small Animal PET Scanner

To address modern molecular imaging requirements, a digital positron emission tomography scanner for small animals has been developed at Universite de Sherbrooke. Based on individual readout of avalanche photodiodes (APD) coupled to a LYSO/LGSO phoswich array, the scanner supports up to 3072 channels in a 16.2 cm diameter, 7.5 cm axial field of view with an isotropic 1.2 mm FWHM intrinsic spatial resolution at the center of the FOV. Custom data acquisition boards sample APD signals at 45 MHz and compute in real time crystal identification, energy and timing information of detected events at rates of up to 1250 raw counts per second per mm2 (10k cps/channel). Real time digital signal analysis also filters out events outside the photopeak with crystal granularity to eliminate Compton events and electronic noise. Retained events are then merged into a single stream through a real-time sorting tree, at which end the prompt and delayed coincidences are extracted. A single Firewire link handles both control and data transfers with a computer. The LabPETtrade features four data recording modes, giving the user the choice to retain data for research or to minimize file size for high coincidence count rate and imaging purposes. The electronic system also supports time synchronized data insertion for flags such as vital signs used in gated image reconstruction. Aside from data acquisition, hardware can generate live energy and discrimination histograms suitable for fast, automatic channel calibration.

Design of a dual-modality, digital positron emission tomography/computed tomography (PET/CT) scanner for small animal imaging

Contemporary PET scanners are commonly implemented with VLSI analog front-end electronics to reduce power consumption, space, noise and cost. Analog processing yields excellent results in dedicated applications, but offers little flexibility for sophisticated signal processing. One design goal of the new Sherbrooke PET/CT scanner is to achieve 1 mm resolution in both emission (PET) and transmission (CT) imaging using the same detection system. One further goal is to be able to use PET detectors and electronics to count and discriminate individual X-ray photons in CT mode. These requirements can be better met by sampling and digitizing the analog signal from each individual channel as early as possible. To meet these requirements, we developed an open digital architecture allowing new technology developments to be incorporated. A specific charge-sensitive amplifier (CSP) satisfying PET and CT needs, a low noise data acquisition system and advanced digital signal processing methods are joined together in order to meet requirements. The hardware is based on standard off-the-shelf 8- bit 100-MHz high-speed analog converters (ADC) and high-performance field programmable gate arrays (FPGA). By implementing 64 channels per board, a 1024-channel PET/CT camera can be created by disposing 16 such modular boards on a ring.

Preliminary results of a data acquisition sub-system for distributed, digital, computational, APD-based, dual-modality PET/CT architecture for small animal imaging

A new highly integrated data acquisition (DAQ) system for a combined, APD-based, dual-modality PET/CT scanner, implementing both analog and digital electronics on the same board, has been fabricated and tested. The DAQ system was designed to achieve high-precision (<1 ns) coincidence detection in PET and high-rate event counting in CT imaging using the same detectors and electronics. One DAQ board holds 64 parallel detector channels that can be sampled directly at the output of the charge-sensitive preamplifiers (CSP) at a rate of 100 MHz with free-running analog-to-digital converters (ADC) from Maxim. Digital signal processing is performed in field programmable gate arrays (FPGAs) from Xilinx. Independent 500 V voltage regulators are mounted on board for optimum biasing of individual APDs coupled to phoswich detectors. The DAQ board has been fabricated on a 12 copper layers printed circuit board (PCB). The low-noise analog front-end is directly interfaced on board through differential CSP outputs to the high-speed digital circuits for optimum coupling and noise immunity. The board shows excellent electrical characteristics with all circuitry powered up, featuring a mean signal to noise and distortion ratio (SINAD) of 47.7 dB over all 64 channels when supplied with a 10 MHz sine waveform at its input. Initial performance characteristics with BGO/LSO phoswich detectors are reported.

A data acquisition sub-system for distributed, digital, computational, APD-based, bimodal PET/CT architecture for small animal imaging

The integration of a positron emission tomography (PET) scanner and a computed tomography (CT) scanner using the same detection system is a real challenge. The goal of the proposed PET/CT scanner design is to achieve high-speed data acquisition with a coincidence time window smaller than 10 ns and less than 1 mm spatial resolution in both PET and CT imaging using the same PET detectors and electronics. Events can be processed at high count-rate, based on a distributed computational architecture mounted directly within the PET ring. To satisfy these new technological requirements, a modular data acquisition sub-system (DASS) was designed, capable of handling up to 64 individual PET/CT detector channels. The DASS is based on off-the-shelf 8-bit, 100-MHz, high-speed free running analog-to-digital converters (ADC) and digital signal processing running on field programmable gate arrays (FPGA). The core of the processing units consists of four Xilinx Spartan-III FPGAs that can hold up to 16 individual channels each. The modular printed circuit board (PCB) has twelve copper layers, allowing separate ground and power planes to be implemented. The PCB outline allows various configurations in a multi-ring stacking geometry to realize 3-D scanners.