F.H. Irons

Using sine wave histograms to estimate analog-to-digital converter dynamic error functions

This paper describes a new method for developing analog-to-digital converter (ADC) error function models using modified sinewave histogram methods. The error models may be used to digitally compensate for nonlinearities introduced by the converter. The histogram modification involves sorting of converter output samples based upon an estimated associated input derivative signal. This error model is based upon a previously unpublished result which shows that sinewave histograms yield distinctly different expected errors for each state based upon input signal slope associated with each output sample. This result thus provides a dynamic dependence for expected errors measured by means of histogram methods. Sorted sinewave histograms are used to estimate slope dependent expected errors at each ADC output state (code). The method provides improved error representation by providing error basis functions for every output code. Simulated results prove that this method removes all slope dependent errors for complex ADC architectures while experimental results for an 8-bit 200 MSPS ADC yielded more than 10 dB improvement in spurious-free-dynamic-range (SFDR) over the full Nyquist band. The new method is thus shown to possess wideband dynamic error character.

The modulo time plot-a useful data aquisition diagnostic tool

This paper illustrates the use of the Modulo Time Plot to facilitate diagnosis of data acquisition systems and components. While conventional techniques, involving spectral analysis and histograms, provide certain useful and necessary measures of performance, the use of reordered sample sets has gained considerable popularity in recent work aimed at characterizing analog-to-digital converter error mechanisms. Examples show that the Modulo Time Plot is useful for quick visual inspection of system performance including dynamic range, distortion and error plots, the detection of random bit errors, and timing errors between the test signal and the sample clock.

The noise power ratio-theory and ADC testing

This paper develops theory behind the noise power ratio (NPR) testing of ADCs. A mid-riser formulation is used for mathematical simplicity. Simulated results, using DAC generated signals, suggests that the uniformly distributed signal is easier to implement and is more sensitive to amplitude dependent distortions.

Distortion compensation for time-interleaved analog to digital converters

A common technique to achieve high sample rates for analog-to-digital converters (ADCs) is to time interleave two or more devices. A drawback of this approach is that mismatches between the devices cause distortion in the sample sequence. This distortion limits the dynamic range which may be achieved using a particular ADC. Although phase-plane compensation techniques exist to improve the dynamic range of ADCs, these techniques are ineffective for time-interleaved structures. This paper extends the existing phase-plane modeling techniques to time-interleaved architectures. The modified algorithms are tested using a 500 MSPS ADC and are shown to reduce harmonic and intermodulation distortion terms by well over 10 dB.

Analog-to-digital converter error diagnosis

Following published procedures for characterizing ADCs using phase-plane error functions, this paper shows how a given calibration data set may used to extract estimates of: specific error performance features pertaining to ADC architectural considerations. The procedure requires the selection of basic functions based upon properties of a desired feature. The techniques are applied to the 8-bit TKAD20 operating at 204.8 MSPS to illustrate the concepts discussed in the paper. Results show how it is possible to estimate hysteresis and average sample time errors versus the state of the ADC. A simple consideration shows why it is not possible to separate sample time errors from the effects of nonlinear capacitance and a first ever diagnosis yields sample-time jitter versus ADC state.

Fast compensation of analog to digital converters

Much research has been done in characterizing error mechanisms and compensating Analog to Digital Converters (ADCs). The process of calibrating the ADCs which evolved from this previous research has generally involved exciting the ADC with as many as 100 different single-tone signals. This paper explores the process and results of calibrating an ADC with as few as two wideband signals. Models of dynamic errors are developed using a harmonic based non-iterative approach. Hardware results show error models capable of compensating the ADC over the full Nyquist band. Simulation results confirm the validity of the algorithm.

Measurement of random sample time jitter for ADCs

This paper addresses the measurement of random sample-time jitter in the characterization of ADCs. A straightforward test is developed which allows for measurement of both additive noise power and RMS sample-time jitter. Simulations are used to assess the accuracy of the technique. Experimental results are also given for a commercially available ADC.

Using adjacent sampling for error correcting analog-to-digital converters

The authors address the use of neighboring samples to linearize the behavior of high-speed flash analog-to-digital converters (ADCs). A novel converter architecture is proposed in which a single flash comparator bank and dual latch/encoder stages allow samples to be taken at intervals much smaller than the sampling period. The result is a calibration/compensation procedure which is less sensitive to calibration frequency than are previous schemes. Using two TRW-1025 converters to implement the architecture shows an improvement in the spurious free dynamic range of between 10 dB and 20 dB over the majority of the Nyquist band.<<ETX>>

Dynamic compensation of digital to analog converters

High accuracy Digital to Analog Converters (DACs) are becoming increasingly important as the use of digital signal processing in communications becomes more common. DACs translate a digital sequence into an analog current or voltage output. This translation is not ideal and the DAC introduces some harmonic error at its output. This paper develops a model for DAC harmonic error explores a lowpass calibration scheme for measuring DAC errors, and develops a scheme for compensation of these errors. Simulated results reveal the system is capable of compensating dynamic DAC errors that produce energy in the lowpass calibration band. Hardware results show that harmonic distortion is reduced using this compensation scheme, but some dynamic errors present in the DAC produce little energy in the calibration band and are not compensated.

Discrete-time dynamic compensation of analog-to-digital converters

The use of post-sampling digital signal processing to linearize the behavior of high speed flash analog-to-digital converters (ADCs) is discussed. Dynamic compensation of the sampled ADC input is achieved by accessing an error correction table using the current state of the converter and an estimate of the derivative of the input signal. A finite impulse response (FIR) filter is used to provide the estimate of the slope of the input signal, resulting in a compensation procedure which may be implemented for any off-the-shelf converter. Performance is shown to be comparable to that obtained using other procedures which require either modifications of the ADC architecture or the use of multiple ADCs.<<ETX>>