F. Raoult

Conduction behaviour of low-temperature (≤600°C) polysilicon TFTs with an in situ drain doping level

The electrical properties of low temperature (≤600°C) polysilicon thin film transistors (TFTs) are investigated as a function of temperature and drain and gate voltage. Two types of TFTs have been processed: Classical in situ Doped Drain TFTs (CDD TFTs) and Lightly in situ Doped Drain TFTs (LDD TFTs). The electrical properties of the TFT can be improved by a reduction of the in situ drain doping level. For instance the OFF state current can be significantly reduced at low drain voltage (Vds<5 V) owing to a reduction of the local electrical field near the drain. Therefore LDD TFTs exhibit a high ON/OFF state current ratio (IONIOFF=4 × 106). For both TFTs the ON state current is well described by the trapping of carriers at grain boundaries located near the interface. In addition for both structures the OFF state current (IOFF) results from various processes of trapped carrier emission at grain boundaries localized in the space charge region of the drain junction, such as pure thermal emission, Poole-Frenkel thermal emission, thermoelectronic field emission, and band to band tunneling emission.

Comparison of the low-temperature (≤600°C) polysilicon thin-film transistors (TFTs) with two kinds of gate dielectrics

Abstract Low-temperature ( ≤ 600 °C) polysilicon thin film transistors (TFTs) were processed with two types of gate insulator: wet oxide/LPCVD Si3N4 double layer and APCVD SiO2 thin film. Electrical performances were analyzed and compared for the two types of TFT. The thermal oxide with LPCVD Si3N4 thin film provides a better gate insulator/poly-Si interface than the gate APCVD SiO2 insulator in terms of effective interface state density, which is approximately ten times lower (NT = 9 − 10 × 10 11 cm−2 eV−1 versus 8 − 9 × 1012 cm−2 eV−1), and in terms of field effect mobility, which is much higher (μ = 58 cm 2 V−1 s−1 versus 6 cm2 V−1 s−1). However, the threshold voltage is higher (VT = 6.5 V versus 5 V) because of a hot carrier trapping effect at the SiO 2 Si 3 N 4 interface. In addition, gate insulation with oxide/nitride is not as good as with APCVD SiO2.

Effects of the in-situ drain doping on hot-carrier degradation in polysilicon thin film transistors

Abstract Hot carrier effects owing to bias stress are studied in two types of polysilicon TFTs: classical in-situ doped drain TFTs and lightly in-situ doped drain TFTs. Two types of bias stress are applied: a negative bias stress corresponding to a negative gate to drain voltage and a positive bias stress corresponding to a positive gate to drain voltage. The positive bias stress induces hot-hole injection into the gate oxide leading to a decrease of the leakage (off state) current and of the threshold voltage, and to an increase of the transconductance in classical in-situ doped drain TFTs. On the other hand, due to a lower local electric field in the drain junction, no significant change is observed in LDD TFTs. However, by stressing TFTs with a negative bias stress, a very large hot-carrier degradation occurs in lightly in-situ doped drain TFTs due to hot electron injection into the gate oxide.

Effect of thickness and granular structure on the electrical conductivity of the active layer in polycrystalline silicon TFTs

The variation of the electrical conductivity of the polycrystalline silicon thin film constituting the active layer of p+pp+ accumulation TFTs is studied as a function of the film thickness. A simple electrostatic model of the study structure and of its silicon layer, associated with a numerical method of solving 2D-Poissons equations, allows to show that the conductivity of the film depends on both carrier trapping at grain boundaries and electrostatic coupling between interfaces, between interfaces and grain boundaries parallel to the Si/SiO2 interface, when they exist, and between parallel and perpendicular grain boundaries.

Electrical conduction phenomena versus temperature in a lateral polysilicon pn junction: analysis and modelling☆

Abstract Lateral pn diodes are fabricated in a polysilicon layer grown by L.P.C.V.D. onto oxidized silicon substrates. The I ( V ) characteristics of these structures are analysed versus temperature. In the case of forward bias, we give evidence of two activation energies, the first one in the high temperature range and the second one in the low temperature range. After having modeled the field effect on the traps, we adapt the current analytical model proposed by Greve to simulate the junction forward and reverse currents for various temperatures. At high temperatures the fitting parameter values ( n and F 0 ) are in agreement with the experimental results and can be explained by an interaction between the trap states and the conduction band. At low temperatures these parameter values appear as the consequence of carrier transitions between neighbouring traps at grain boundaries.

Characterization of the polysilicon thin film transistors elaborated in high and low temperature processes. Study of the density of traps

Abstract The states density of traps (DOS) in the gap has been determined by a study of the temperature influence on the field-effect conductance of polycrystalline silicon thin film transistors fabricated in high and low temperature technologies. The effect on the DOS value of the granular structure, film thickness (between 50 and 150 nm) and technological process has been investigated. On the one hand, for thin film transistors (TFTs) fabricated in a high temperature process, we observed that, when the film thickness is greater than 50 nm, the DOS distribution has a ‘band tailing’ with an exponential shape. The slope increases when the thickness decreases. This indicates the enhancement of the disorder due to an important density of defects localized in the grain and or in the grain boundaries. Moreover, for thin films ( t f = 50 nm), the DOS curve shows a characteristic hump which proves the presence of dangling bonds. They are localized at 0.35 eV above the top of the valence band. On the other hand, the effect of the low temperature process produces particularities on the TFT DOS. The classical doped drain (CDD) exhibits a high density of states with a classical distribution (band tailing with an exponential shape). However, the lightly doped drain (LDD) TFT DOS shows a hump localized at 0.4 eV below the bottom of the conduction band. The difference observed on the DOS distributions is related to the in situ doping level of the polysilicon-deposited thin films.

The analysis of the leakage current of polycrystalline silicon thin-film transistors as a function of active layer thickness

The variation of electrical conductivity and generation current in the active layer of polycrystalline silicon thin-film transistors (TFTs) was analysed as a function of the thickness of this layer. A simple model for the active layer and numerical solution of Poissons equation in two dimensions has shown that the electrical conductivity, together with the generation current, does depend on the carrier traps at the grain boundaries and on the electrostatic coupling between the oxide/silicon interface or between the interfaces and the parallel grain boundary when present.

Effect of the active layer thickness on the leakage current in p+p p+ accumulation polycrystalline silicon TFTs

Abstract The variations of the resistive and generation components of the leakage current in p+p p+ accumulation polycrystalline silicon TFTs as functions of the active film thickness are analyzed. A simple electrostatic model of the studied structure and of its silicon layer, associated with a numerical method of solving the 2D Poisson equation, allows us to show that the resistivity of the film and the electric field-enhanced generation current depend on both carrier trapping at grain boundaries and electrostatic coupling between interfaces, between interfaces and parallel grain boundaries, when they exist, and between parallel and perpendicular grain boundaries.