F. Volpi

Copper-Line Topology Impact on the Reliability of SiOCH Low-

SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub-45-nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With line-to-line spacing reduction, the control of the line shape and of the spacing uniformity within a wafer is becoming first-order parameters governing the low- k dielectric reliability. Improving the low- k reliability requires to discriminate each topological effect and to quantify its impact on the lifetime at product level. This paper demonstrates that the copper line shape induces a preferential breakdown of the dielectric close to the SiOCH/SiCN capping even at nominal voltage. The impact of the line edge roughness is studied with the introduction of a simple analytical model. Moreover, the impact of the roughness on the product lifetime has been quantified. It is demonstrated that the line-to-line spacing variation is less critical at the operational voltage than at high voltage stress. Finally, the impact of the spacing uniformity within the wafer and from wafer to wafer (reflecting the spacing fluctuation from product to product) on the Weibull shape is quantified and reported to be voltage-dependent in agreement with the experimental detail.

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SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.

for the 45-nm Technology Node and Beyond

The present paper compares the effects of AC and DC electrical stress on low-κ SiOCH and high-κ ZrO2 and Ta2O5 back-end dielectrics. A wide panel of stress conditions has been assessed, mixing DC, unipolar/bipolar and relaxation times. The DC-stress being the reference stress condition, no enhancement of the time-to-breakdown (TBD) has been found with pure bipolar stress. On the contrary unipolar stress showed a strong improvement of this characteristic. We propose that the lifetime enhancement is due to a charge detrapping mechanism within the dielectric that affects the defect density. Under unipolar- and relax-bipolar-stress the time-to-breakdown has been corrected by the duty cycle in order to consider the effective duration of the stress. In this study no impact of copper has been found on the breakdown behaviour.

Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime

Porous low-k dielectrics reliability in interconnect is a major concern for sub 45 nm technology nodes. Low-k dielectric ageing characterization during stress is becoming a key point to improve low-k interconnect robustness. In this context, the leakage and especially the capacitance shifts under electrical stress are analyzed in this paper. Four dielectric ageing mechanisms potentially responsible of the capacitance drift during stress are discussed and compared to experiments. Donor trap creation leading to the I(V) sweep variation is confirmed with leakage activation energy measurement during the stress. Moreover, the capacitance shift could be due to a trapping/detrapping charge into pre-existing or created traps.

Back-end dielectrics reliability under unipolar and bipolar AC-stress

This paper reports results obtained on a new test structure developed to easily locate low-k dielectric breakdown spots. This spot can be localized by using a comb-serpentine test structure, and by monitoring the change in resistance between pads.