F. Wafula

All electrochemical fabrication of a platinized nanoporous Au thin-film catalyst.

In an effort to decrease the high cost associated with the design, testing, and production of electrocatalysts, a completely electrochemical scheme has been developed to deposit and platinize a nanoporous Au (NPG) based catalyst for formic acid oxidation. The proposed route enables synthesis of an alternative to the most established, nanoparticles based catalysts and addresses issues of the latter associated with either contamination inherent from the synthetic route or poor adhesion to the supporting electrode. The synthetic protocol includes as a first step, electrochemical codeposition of a Au((1-x))Ag(x) alloy in a thiosulfate based electrolyte followed by selective electrochemical dissolution (dealloying) of Ag as the less noble metal, that generates an ultrathin and preferably continuous porous structure featuring thickness of less than 20 nm. NPG is then functionalized with Pt (no thicker than 1 nm) by surface limited redox replacement (SLRR) of underpotentially deposited Pb layer to form Pt-NPG. SLRR ensures complete coverage of the surface with Pt, believed to spread evenly over the NPG matrix. Testing of the catalyst at a proof-of-concept level demonstrates its high catalytic activity toward formic acid oxidation. Current densities of 40-50 mA cm(-2) and mass activities of 1-3 A.mg(-1) (of combined Pt-Au catalyst) have been observed and the Pt-NPG thin films have lasted over 2600 cycles in standard formic acid oxidation testing.

Toward a Better Understanding of the Effect of Cu Electroplating Process Parameters on Cu3Sn Voiding

“Kirkendall voiding” in the interfacial Cu3Sn intermetallic compound is often observed in solder joints made between Sn-containing alloys and Cu interconnect pads, during extended thermal aging or electromigration testing. It is commonly believed that voids arise from the Kirkendall effect, i.e., the imbalance of diffusion fluxes of Cu and Sn atoms in Cu3Sn. However, recent studies have demonstrated that the propensity for voiding is greatly affected by the amount of organic impurities incorporated during Cu electroplating. The level of impurities was shown to depend on various electroplating parameters, such as current density, bath temperature, bath age, etc. In this study, a general picture is proposed to provide a better understanding of the effect of electroplating process parameters on Cu3Sn voiding. The picture correlates the level of impurity incorporation to (1) the applied electroplating overpotential, and (2) the crystallographic orientation of the Cu deposit. As a first-order approximation, the picture is supported by a variety of electroplating experiments, secondary-ion mass spectroscopy (SIMS), and x-ray diffraction (XRD) analysis.

Controlling Cu electroplating to prevent sporadic voiding in Cu 3 Sn

One reliability concern, when soldering to a Cu surface finish, is the sporadic mechanical degradation of solder joints due to the formation and growth of voids within the interfacial Cu3Sn intermetallic compound (IMC) layer and at its interface with the Cu pad structure. Excess organic impurity incorporation during Cu electroplating has been shown to cause this problem. The level of impurity incorporation is found to depend greatly on interactions between the plating additive chemistry and the plating process parameters. A general picture has been developed, based upon the parabolic adsorption behavior of organic molecules on metal electrodes in aqueous plating solutions as a function of the applied potential. Thus the propensity for voiding, in soldering and subsequent thermal aging, can be manipulated by varying a range of plating parameters. The mechanistic understanding required to devise practical control is outlined. Any remaining research required for the formulation of step-by-step process guidelines is identified.

Understanding, Controlling and Minimizing the Voiding, Sporadically Occurring in Solder Joints with Electroplated Copper

The present work offers generic remedies for a problem that is known to have cost the industry billions of dollars. When an interconnect is made between typical Sn containing solder and Cu pads, metallurgical reactions lead to the formation of Cu6Sn5 and Cu3Sn intermetallic compounds (IMC), as seen in Figure. Right after reflow the latter is usually extremely thin, but both grow subsequently by solid state reactive diffusion processes. On rare occasions the Cu3Sn intermetallic compound formed with specific electroplated Cu samples has been seen to develop voids and weaken to a catastrophic extent over time near or at room temperature. More commonly voids have been seen to grow in accelerated thermal aging and cause wear out or fatigue life degradation in board level testing [1, 2].