Fa Wang

Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Efficient high-dimensional performance modeling of todays complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient high-dimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9× runtime speedup over the traditional modeling technique without surrendering any accuracy.

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75× runtime speedup over the traditional kernel estimation method.

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate on-chip performance measurement. A 25GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is improved from 0% to 69.17% for a wafer after the proposed self-healing is applied.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuits increasingly susceptible to large-scale process variations. On-chip self-healing has been proposed as a promising remedy to address the variability issue. The key idea of on-chip self-healing is to adaptively adjust a set of on-chip tuning knobs (e.g., bias voltage) in order to satisfy all performance specifications. One major challenge with on-chip self-healing is to efficiently implement on-chip sensors to accurately measure various analog and RF performance metrics. In this paper, we propose a novel indirect performance sensing technique to facilitate inexpensive-yet-accurate on-chip performance measurement. Towards this goal, several advanced statistical algorithms (i.e., sparse regression and Bayesian inference) are adopted from the statistics community. A 25 GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32 nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is significantly improved for a wafer after the proposed self-healing is applied.

Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits

In this paper, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AMS) circuits with consideration of large-scale process variations. The BMF technique is motivated by the fact that todays AMS design cycle typically spans multiple stages (e.g., schematic design, layout design, first tape-out, second tape-out, etc.). Hence, we can reuse the simulation and/or measurement data collected at an early stage to facilitate efficient validation and tuning of AMS circuits with a minimal amount of data at the late stage. The efficacy of BMF is demonstrated by using several industrial circuit examples.

Large-scale statistical performance modeling of analog and mixed-signal circuits

The aggressive scaling of IC technology results in large-scale performance variations that cannot be efficiently captured by traditional modeling techniques. This paper presents the recent development of statistical performance modeling and its important applications. In particular, we focus on two core techniques, sparse regression (SR) and Bayesian model fusion (BMF), that facilitate large-scale performance modeling with low computational cost. The basic ideas of SR and BMF are first explained and then their efficacy is compared to other traditional modeling approaches by using several analog and mixed-signal circuit examples.

Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information

Efficient performance modeling of todays analog and mixed-signal (AMS) circuits is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Co-Learning Bayesian Model Fusion (CL-BMF). The key idea of CL-BMF is to take advantage of the additional information collected from simulation and/or measurement to reduce the performance modeling cost. Different from the traditional performance modeling approaches which focus on the prior information of model coefficients (i.e. the coefficient side information) only, CL-BMF takes advantage of another new form of prior knowledge: the performance side information. In particular, CL-BMF combines the coefficient side information, the performance side information and a small number of training samples through Bayesian inference based on a graphical model. Two circuit examples designed in a commercial 32nm SOI CMOS process demonstrate that CL-BMF achieves up to 5× speed-up over other state-of-the-art performance modeling techniques without surrendering any accuracy.

DREAMS: DFM rule EvAluation using manufactured silicon

DREAMS (DFM Rule EvAluation using Manufactured Silicon) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of DFM (design for manufacturability) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically-aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits

This paper presents a design methodology of millimeter-wave circuits that are insensitive to process, voltage, and temperature variations. Instead of using conventional direct sensing, the authors propose an indirect sensing method with Bayesian fusion, which simplifies the sensors and allows more adaptive circuit loops to be integrated.

A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration

A self-healing mmWave SoC integrating an 8052 microcontroller with 12kB of memory, an ADC, a temperature sensor, and a 3-stage cascode 60GHz LNA, implemented in a 32nm SOI CMOS technology exhibits a peak gain of 21dB, an average 3.3dB NF from 53 to 62GHz and 18mW power consumption. An indirect NF sensing algorithm was implemented on the integrated uC, which enables an adaptive biasing algorithm to reduce the 60GHz NF sigma and LNA power consumption by 37 and 40%, respectively, across P,V,T.