Fabian Wolf

Path clustering in software timing analysis

Verification of program running time is essential in system design with real-time constraints. Simulation with incomplete test patterns or simple instruction counting are not appropriate for complex architectures. Software running times of embedded systems are process state and input data dependent. Formal analysis of such dependencies leads to software running time intervals rather than single values. These intervals depend on program properties, execution paths, and states of processes, as well as on the target architecture. An approach to analysis of process behavior using running time intervals is presented. It improves our previous work by exploiting program segments with single paths and by taking the execution context into account. The example of an asynchronous transfer mode (ATM) cell handler demonstrates significant improvements in analysis precision. Experimental results show the superiority of the presented approach over well-established approaches.

Execution cost interval refinement in static software analysis

Embedded system software timing and power consumption or, in general, execution costs are state- and input-data dependent. Therefore, formal analysis of such dependencies leads to execution cost intervals rather than single values. These intervals depend on system concurrency, execution paths and process states, as well as on target architecture properties. This paper presents an approach to modeling and analysis of process behavior using intervals. Unlike other static software analysis approaches, it considers program properties and the execution context, i.e. the current state and input of a process. The example of an ATM switch component demonstrates significant improvements in analysis precision.

Intervals in software execution cost analysis

Timing and power consumption of embedded systems are state and input data dependent. Formal analysis of such dependencies leads to intervals rather than single values. These intervals depend on program properties, execution paths and states of processes, as well as on the target architecture. This paper presents an approach to analysis of process behavior using intervals. It improves previous work by exploiting program segments with single paths and by taking the execution context into account. The example of an ATM cell handler demonstrates significant improvements in analysis precision.

Hybrid Cache Analysis in Running Time Verification of Embedded Software

Verification of software running time is essential in embedded systemdesign with real-time constraints. Simulation with incomplete test patternsis unsafe for complex architectures when software running times are inputdata dependent. Formal analysis of such dependencies leads to software runningtime intervals rather than single values. These intervals depend on programproperties, execution paths and states of processes, as well as on the targetarchitecture. In the target architecture, caches have a major influence onsoftware running time. Current cache analysis techniques as a part of runningtime analysis approaches combine basic block level cache modeling with explicitor implicit program path analysis. We present an approach that extends instructionand data cache modeling from basic blocks to program segments thereby increasingthe overall running time analysis precision. We combine it with data flowanalysis based prediction of cache line contents. This novel cache analysisapproach shows high precision in the presented experiments.

Data flow based cache prediction using local simulation

Accurate cache modeling and analysis are crucial to formally determine program execution time. Current cache analysis techniques combine basic block level cache modeling with explicit or implicit program path analysis. We show how to extend program and data cache modeling from basic blocks to program segments thereby increasing the overall execution time analysis precision. The approach combines architecture simulation, data flow analysis and implicit path enumeration.

Timing and power measurement in static software analysis

Evaluation boards are popular as prototyping platforms in embedded software development. They are often preferred over simulation to avoid modeling effort and simulation time as well as over complete hardware prototypes to reduce development cost. The paper presents the application of a commercial logic state analyzer for timed trace acquisition with instruction cycle accurate software power measurement on commercial evaluation kits. The results are applied in an instruction level software power analysis technique. Both approaches can be used for segment-wise architecture modeling in static software analysis approaches.

Interval-Based Analysis of Software Processes

A typical characteristic of complex embedded systems is their large software share that consists of software processes either being directly written in an implementation language like C, or being created from abstract modeling tools (e. g. Simulink or StateMate) using standard code generators, or being reused from previous designs (e. g. legacy code). A major challenge is the safe integration of these separately designed system parts. This paper focuses on the formal analysis of software processes with respect to their non-functional properties like timing or power consumption. The proposed approach yields safe upper and lower bounds on these properties and has advantages over previous work in terms of accuracy and efficiency. Further, it is shown how the results of this process-level analysis can be utilized to generate a model for the system-wide validation of non-functional properties. The applicability of the approach is demonstrated using an example of a filter process operating on a packet stream.

Compact trace generation and power measurement in software emulation

Evaluation boards are popular as prototyping platforms in embedded software development. They often are preferred over simulation to avoid modeling effort and simulation times as well as over compete hardware prototypes to avoid development cost. Evaluation boards provide accurate timing results as long as the main architecture parameters match the target hardware system. For larger processors, this is often not the case since the cache and main memory architectures might differ. Another problem is the lack of observability of the software execution. Pin-Out versions of processors with improved observability are expensive and not always available, and on-chip processor test support requires software adaption. A particular problem arises when trying to verify the running time bounds of embedded software such as required for hard real-time systems. Here, formal analysis approaches have been proposed which require segment-wise execution of a program under investigation. Another problem is the accurate analysis of processor power consumption for different execution paths.

System exploration and synthesis from SDL of an ATM switch component

We describe the complete hardware synthesis of an ATM switch component, characterized by concurrent and dynamic processes, very high bit-rate data streams, and intensive data storage and transfer. The methodology used to synthesize it bridges the gap between an SDL system specification and an optimized single-chip implementation of communicating hardware processors, that satisfies stringent constraints on area, performance, and power. The novelty of this methodology is that through stepwise exploration, and gradual incorporation of timing constraints, it supports new optimization methods in view of memory and concurrency management, and expensive late iterations are avoided.

Dynamic memory management methodology applied to embedded telecom network systems

Presents a new methodology for dynamic memory management of embedded telecom network systems. This methodology enables the designer to further raise the abstraction level of the initial system specification and to achieve optimized embedded system designs. This methodology is well suited for systems characterized by a set of concurrent and dynamic processes, very high-bit-rate data streams, and intensive data transfer and storage, as encountered in telecom network applications. Up to now, it has been successfully applied to four telecom network systems. This methodology can be easily integrated into any C++-based system synthesis approach that bridges the gap between a concurrent process-level system specification and an optimized (for area, performance, or power) embedded implementation of communicating hardware/software processors. This is in contrast to current system design practice, where VHDL/C is derived without room for exploration, refinement, and verification, leading to expensive late design iterations. In this paper, the main focus lies on the system-level specification model and the dynamic memory management applied to two real-life telecom network systems.