Fabio Ancona

Implementing Probabilistic Neural Networks

A modified PNN training algorithm is proposed. The standard PNN, though requiring a very short training time, when implemented in hardware exhibits the drawbacks of being costly in terms of classification time and of requiring an unlimited number of units. The proposed modification overcomes the latter drawback by introducing an elimination criterion to avoid the storage of unnecessary patterns. The distortion in the density estimation introduced by this criterion is compensated for by a crossvalidation procedure to adapt the network parameters. The present paper deals with a specific realworld application, i.e. handwritten character classification. The proposed algorithm makes it possible to realise the PNN in hardware and, at the same time, compensates for some inadequacies arising from the theoretical basis of the PNN, which does not perform well with small training sets.

Parallel VLSI architectures for cryptographic systems

This paper describes a parallel VLSI implementation of a private-key cryptographic system based on Peano-Hilbert curves. The basic unit of the VLSI architecture is the Crypto Processor, that is an SIMD composed of a grid of 256/spl times/256 processing units performing elementary operations of encoding process. The key length of the system, measured as number of free parameters, depends linearly on hardware complexity: the cryptographic system is modular and its implementation is very cheap. The CP has been implemented as a single chip with a 1-micron CMOS technology and shows a working frequency of 30 MHz. The chip can be used in consumer applications as well as add-on whenever a certain degree of safety in communication is required.

Parallel architectures for vector quantization

The paper describes a parallel implementation of neural networks based on vector quantization. A toroidal-mesh topology has been used to assess the overall approach. A theoretical analysis of the modular systems efficiency is presented. The final application goal is a lossy compression of high-dimensional data for low bit-rate communications. Experimental results on a significant testbed shows a remarkable increase of the systems performances. In addition, the fit between predicted and measured efficiency values confirms the validity of the overall theoretical model.

VLSI architectures for programmable sorting of analog quantities with multiple-chip support

The paper describes VLSI architectures for sorting analog quantities. The elementary circuit unit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design and enables multi-chip integration. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.

A parallel approach to plastic neural gas

A parallel implementation of unsupervised vector-quantization networks can reduce the high computational load of the training process. First, a plastic version of the neural gas algorithm is presented. Then, the paper describes how a toroidal mesh topology fits the neural model for a distributed implementation. The architecture adopted and the data-allocation strategy enhance the methods scaling properties and remarkable efficiency. Experimental results on a significant testbed (low bit-rate image compression) confirm the validity of the parallel approach.

An efficient technique for implementing an image-compression neural algorithm on concurrent multiprocessor architectures

Abstract The paper describes a parallel implementation of a neural algorithm performing vector quantization for very low bit-rate video compression on toroidal-mesh multiprocessor systems. The neural model considered is a plastic version of the Neural Gas algorithm, whose features are suitable for implementations on toroidal mesh topologies. The architecture adopted, and the data-allocation strategy, enhance the methods scaling properties and remarkable efficiency. The parallel approach is supported by a theoretical analysis of the efficiency of the overall structure. Experimental results on a significant testbed and the fit between predicted and measured values confirm the validity of the parallel approach.

Hardware implementation of the neural gas

The paper presents a hardware implementation of the neural gas (NGAS) algorithm. The NGAS is based on vector quantization and is applied to very low bit-rate video compression. The algorithm exhibits interesting properties that can be exploited in an HW realization. The modular structure provides inherent parallelism and can therefore be regarded as an open architecture. The neuro-board interfaces to a PC through a standard ISA bus. The novelty of the proposed solution lies in providing a PC-based configurable HW support for VQ training joining affordable costs with satisfactory effectiveness. Simplicity and easy control for HW tests and SW development represent the basic advantages of the overall approach.

Concurrent VLSI architectures for vector quantization

The paper describes a methodology to implement vector quantization based neural networks on concurrent VLSI architectures. A toroidal-mesh topology has been used to assess the overall approach. A theoretical analysis of the modular systems efficiency is presented. Experimental results on a significant testbed (low bit-rate image compression) shows a remarkable increase of the systems performances. In addition, the fit between predicted and measured efficiency values confirms the validity of the overall theoretical model.

A vector quantization circuit for trainable neural networks

Vector quantization systems are usually implemented in hardware by realization of an algorithm, usually exploiting accelerated techniques for codebook search. These implementations are not well suited for the use as analog electronic neural networks building blocks. This paper presents an analog, fully parallel implementation of vector quantization exploiting a large number of simple processors. The circuit features large-dimensional (64) vectors and a medium-to-high density of units per chip. Moreover, the winner-take-all block features a linear output that replicates the value of the winning distance, in addition to the winners location flag. This makes it possible to use the system in trainable networks without need for further circuitry.

Hypercube structures with high-connectivity supporting nodes

Abstract Hypercubes represent an important class of architectures for parallel computation, thanks to their remarkable interconnection features. The paper examines a hypercube system supported by high-connectivity processing nodes. The basic element, called “complex node”, integrates two transputers by a dual-port memory and supports a total of eight links. Therefore, the node allows one to build a seven-dimensional hypercube with 128 nodes. The paper also presents a routing algorithm that has been suitably developed to fit the node performance, and manages traffic over the network. The performance of the router has also been evaluated experimentally.