Fabio Campi

Design and Implementation of a Power-aware FFT Core for OFDM-based DSA-enabled Cognitive Radios

This research work presents the design and the physical implementation of a power aware FFT core for OFDM-based, dynamic spectrum access (DSA) enabled cognitive radios. The FFT core is equipped with a pruning engine that allows the run-time removal of dummy operations (e.g. multiplications by a zero term) related to the pruning of sub-carriers of the communication systems. The pruning algorithm introduced by this research work utilizes a reduced size configuration matrix, which limits the memory requirements’ overhead. Finally, the physical implementation of the FFT on a 45 nm technology node showed that, for a 8 % area overhead, the total power saving settles around 10 % when in the presence of a medium to high pruning level, justifying the silicon area overhead introduced by the pruning unit.

Multi-functional capacitive proximity sensing system for industrial safety applications

This paper presents a capacitive sensing system, addressing the issue of collision avoidance in partially modelled or unknown robot-assisted industrial environment by means of object distance measurement, motion tracking, and surface profile detection. The sensor consists of a mesh of multiple electrodes, a digital control module, a capacitance to digital converter, and a data processing module. The mesh is composed of 16 metal squares organized to form a 4×4 capacitor matrix. The electrode connections within the matrix can be reconfigured at run time by the digital control logic to provide multiple sense functionalities. Statistical regression models are applied to derive the distance and track the motion. A machine learning algorithm (Support Vector Machine, SVM) is applied to measured data to classify surface profiles. The fabricated sensing system has the ability of detecting objects at distances up to 20 cm from the sensor, and shows accuracy over 90% in profile recognition.

Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization

Multi-mode and multi-standard connectivity has become a necessity for portable communication systems. A convenient architectural solution is to build flexible systems that can be reprogrammed to meet requirements of multiple standards. One of the major issues in this context is the resource overhead required by programmability. In particular, in the latest VLSI technology nodes, energy consumption has become a very severe problem, greatly impacting the reliability of the hardware. Therefore, any design aimed at the implementation of multi-mode multi-standard communication systems must be strictly targeted at the lowest power consumption without jeopardizing peak performance, while, at the same time, retaining a high degree of flexibility. This work presents the design and implementation of a (auto)correlator block for timing synchronization. The design is composed of a scalable computational unit, which allows to meet real-time requirements of different wireless communication standards (e.g. W-CDMA, IEEE 802.11a/g/n). Moreover, dynamic power management allows to dynamically trade-off energy consumption versus performance, adapting power dissipation to the specific requirements of each supported standard, as well as to follow dynamic variations of the computation load.

Programming Tools for Reconfigurable Processors

The capability to tailor the processor instruction set architecture (ISA) around the computational requirements of a given application is proposed today as the most appealing way to match performance with very short time-to-market, accomplishing the reduction of non-recurring engineering (NRE) costs. From Mask-Time Configurable Processors (MTCPs) to Run-Time Reconfigurable Processors (RTRPs), the ISA customization is performed “moving” kernels of initial code from software to hardware, thus introducing a design space exploration problem involving skills in both software and hardware design. Since adaptive processors appear as the natural extension of Digital Signal Processors (DSPs), programming tools for customizable processors need to be as similar as possible to standard software development environments, in order to enable the adaptive computing to the wide audience of DSP programmers. While fast design-space explorations can be performed using high-level description languages, programmers proficient in hardware design can further improve the performance through “structural” descriptions involving, for example, the direct utilization of macro-operators or the possibility of balancing critical paths through register insertion. The widespread knowledge of the ANSI C among developers suggests its usage as main entry language for both configurable and reconfigurable architectures, thus introducing the problem of translating C codes (or C dialects) into some kind of hardware description, be it HDL in case of MTCPs or bit-stream for RTRPs. In this context, Data-Flow Graphs (DFGs) can be efficiently used to close the gap between hardware and software design, thus representing the most natural bridge between the hardware and software descriptions. Furthermore, standard ANSI C can be used by the programmer for the management of the application control flow on the processor core, embedding custom-designed instructions in

Power-Shaping Configurable Microprocessors for IoT Devices

The “Internet of Things” implies a pervasive diffusion of “IoT processors”: small mixed-signal ICs, containing specific sensing/actuating logic coupled to embedded microprocessor core(s) for control, communication, and information processing. IoT processors must be small, low cost, low power, and highly reliable in order to be embedded in remote, often inaccessible locations. Most of all, they must sustain time-varying computation loads, dictated by real time events in the environment they are embedded in. This chapter introduces design strategies for “Power-Shaping Microprocessor Systems”: with relatively limited design overhead, processor systems can be composed by independent, asynchronous clock, voltage and substrate bias islands. Depending on the relative workload of each section, each component in the processor system can be dynamically tuned to the smallest consumption level that still meets real time specification. Such option offers performance boost in the range of 30 %, and decrease in power consumption in the range of 70 %, with area overheads in the range of 5–10 % depending on the design environment. It also enables a mitigation of a rough factor of 5 in current peaks/gradients on the supply lines of each IC. This result is highly relevant, since current gradients are a significant cause of unreliability on CMOS circuits, especially in mixed analog/digital environments such as IoT processors.

Introducing IC reliability elements in digital circuits and systems design education

With the latest advances in technology scaling, reliability of IC design has emerged as an issue of significant concern in the VLSI design community. Reliability is a global concept that needs to be challenged with a system-level approach: all disciplines in circuit and systems education are steadily introducing reliability aspects in their coursework. Still, engineers need to be educated to a holistic view that must include in one context all different aspects of a digital system (analog / digital / packaging / board / software). This work describes an attempt at increasing the coverage and efficacy of this specific learning outcome in digital design courses, introducing a new tool and a new set of lab assignments on top of “standard” digital design flows introduced in previous offerings.

Feasibility of Support Vector Machine gesture classification on a wearable embedded device

This study looks at the need for a device that monitors upper extremity movements. The device needs to be able to predict gestures on-board to provide immediate feedback. Linear Discriminate Analysis and Support Vector Machine Light and Support Vector Machine Multiclass libraries were implemented on an Atmel embedded system to investigate the limitations. For the Support Vector Machine Light implementation the peak memory usage was 2 Mb and used a sample size of 20 samples per class. The implementation of Support Vector Machine Multiclass with 5 classes, had peak memory usage of 1 Mb and 20 samples per class. The work presented here establishes the ground work for creating a standalone device with on-board classification.

Design of digital modules for capacitive proximity sensing system applications

Design of an intelligent controlling module as well as the signal processing module for a novel capacitive proximity sensing system for robotic applications are proposed. The capacitive sensor is composed of a 4×4 matrix of electrodes. The intelligent controlling module is mapped on an FPGA device embedded in the robotic unit; and is utilized to realize various different sensing arrangements within the same electrode matrix. The signal processing module is realized on an external computer and is used to properly process and classify the results produced by the sensor. By involving these two digital components, a rough estimation of obstacles facing the robot unit carrying the sensor and relative accurate distance information from the obstacle can be obtained.

Accomodating the fast-paced evolution of VLSI in engineering curricula

The strength of VLSI education has traditionally been its strict synergy with industry. Today, the evolution of the semiconductors industry, especially in its quest for low-power awareness, requires today a strong synergy between system and physical issues. As a consequence, VLSI design courses may need to increase their focus on system-related issues and the exploration of the impact if physical design on power versus performance tradeoffs. This will represent an exciting opportunity as professional figures such as system architects and embedded software programmers will be more interested in exposure to VLSI concepts. To meet the requirements of a new, and possibly more numerous generation of students, VLSI education also may need to renew its design lab offering, exploiting new practices and communication means that already are common practice in the students population and standardized in industry.

Approximate computing for complexity reduction in timing synchronization

This paper presents the design and performance evaluation of a reduced complexity algorithm for timing synchronization. The complexity reduction is obtained via the introduction of approximate computing, which lightens the computational load of the algorithm with a minimal loss in precision. Timing synchronization for wideband-code division multiple access (W-CDMA) systems is utilized as the case study and experimental results show that the proposed approach is able to deliver performance similar to traditional approaches. At the same time, the proposed algorithm is able to cut the computational complexity of the traditional algorithm by a 20% factor. Furthermore, the estimation of power consumption on a reference architecture, showed that a 20% complexity reduction, corresponds to a total power saving of 45%.