Fahad Mirza

Effect of Through-Silicon-Via Joule Heating on Device Performance for Low-Powered Mobile Applications

Three-dimensional (3D) through-silicon-via (TSV) technology is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. TSVs provide high speed signal propagation due to reduced interconnect lengths as compared to wire-bonding. The current flowing through the TSVs results in localized heat generation (joule heating), which could be detrimental to the device performance. The effect of joule heating on per

Impact of replacing Sn-Ag bumps with Cu pillars on the BEoL Cu/Low-k fracture under reflow - a computational study

Replacing Silicon Dioxide (SiO2) with low-k and ultralow-k (ULK), as a dielectric, in the Back-End-Of-Line (BEoL) has allowed the trend of miniaturization and convergence to continue. Although using low-k and ULK greatly increases the device performance, being mechanically weak these dielectric materials pose a serious challenge from the reliability standpoint. Delamination along the metal-dielectric interfaces and crack propagation in the dielectric layers has been widely observed during cooling from higher temperatures and thermal excursions. Moreover, as scaling of components continues, higher density interconnects and pitch <; 130μm are needed and manufacturers are focusing on copper (Cu) pillars to achieve tighter pitches. Therefore, there is a need to investigate the effect of replacing solder bumps with Cu pillars on the fracture behavior of the BEoL dielectric. This provides the impetus for this work. In this study, a 3D finite element (FE) fracture analysis is performed to demonstrate the thermo-mechanical response of the BEoL region of a flip chip package with Cu pillars (CuP). Crack propagation in the low-k layers is analyzed under the loading when the die is attached to the substrate (reflow). J-integral obtained from the FE analysis is utilized to quantify the impact of replacing solder bumps with Cu-pillars in future high density portable devices.

Performance optimization of multi-core processors using core hopping - thermal and structural

As the work load on the single core processor increases, its power density and the die temperature increases as well. The increase in the die temperature results in decreased performance, reliability and increased leakage currents and cooling cost. Also, the non-uniform power distribution across the die results in hot spots. In order to decrease the work load and the cooling cost on the single core processor, multi-core processors have been implemented. Multicore Processors also known as Chip Multi Processors (CMPs). CMPs are processors which contain two or more independent cores on a chip. In CMPs, if one core reaches its critical temperature, the workload is transferred to the other. This phenomenon is termed as core hopping. Core hopping facilitates uniform distribution of the work load among the many cores and leads to improvements in the performance and reliability. The demand for greater performance in applications involving high levels of computing has resulted in many cores being put on a single chip. Every succeeding processor is predicted to hold double the number of cores than the previous one. In this study, core hopping for CMPs is analyzed and the thermal analysis of the chip with core hopping is performed using ANSYS Fluent. The hop sequence is analyzed as a function of chip temperature distribution and a numerical methodology to analyze the coupled thermal and structural integrity of the CMPs is demonstrated.

Parametric thermal analysis of TSVs in a 3-D module based on interconnect delay and silicon efficiency

The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. 3-D chip stacking is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology is the trend for future electronics, especially hand-held, hence, making it an important research area. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide better inter-chip and chip-substrate electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. TSV is one of the key enabling technologies for 3-D systems. TSVs allow 3-D chips to be interconnected directly and provide high speed signal processing. Electrical interconnection and heat dissipation improves with the number of TSVs. But, there is a trade-off; silicon efficiency of a 3-D package decreases with the TSV count. There are studies for thermo-mechanical analysis of TSVs both at wafer and package level but there is limited data on the electrical aspects of TSVs, i.e., effect of TSV temperature and layout/size on the interconnect delay. In this paper, interconnect delay is determined for various TSV configurations at the package level. Interconnect delay is primarily driven by the interconnect size and temperature. The objective of this work is to determine the optimal number/size of TSVs as a function of silicon efficiency, junction temperature and the interconnect delay. Chip real estate (CRE) - actual chip area available to lay down devices, is varied from 98% to 96% with an interval of 2% (2 cases). For each CRE case, sub-cases are formulated by varying the TSV count/size (keeping the CRE constant) and chip temperature and the interconnect delay is determined and compared. It is seen that for all the TSV configurations at constant CRE, the junction temperature remains constant, however the interconnect delay varies significantly. The work provides design guidelines based on CRE, junction temperature and the interconnect delay for varied applications in the electronics industry.

Investigation of human-robot interface performance in household environments

Today, assistive robots are being introduced into human environments at an increasing rate. Human environments are highly cluttered and dynamic, making it difficult to foresee all necessary capabilities and pre-program all desirable future skills of the robot. One approach to increase robot performance is semi-autonomous operation, allowing users to intervene and guide the robot through difficult tasks. To this end, robots need intuitive Human-Machine Interfaces (HMIs) that support fine motion control without overwhelming the operator. In this study we evaluate the performance of several interfaces that balance autonomy and teleoperation of a mobile manipulator for accomplishing several household tasks. Our proposed HMI framework includes teleoperation devices such as a tablet, as well as physical interfaces in the form of piezoresistive pressure sensor arrays. Mobile manipulation experiments were performed with a sensorized KUKA youBot, an omnidirectional platform with a 5 degrees of freedom (DOF) arm. The pick and place tasks involved navigation and manipulation of objects in household environments. Performance metrics included time for task completion and position accuracy.

Multi-modal sensor and HMI integration with applications in personal robotics

In recent years, advancements in computer vision, motion planning, task-oriented algorithms, and the availability and cost reduction of sensors, have opened the doors to affordable autonomous robots tailored to assist individual humans. One of the main tasks for a personal robot is to provide intuitive and non-intrusive assistance when requested by the user. However, some base robotic platforms can’t perform autonomous tasks or allow general users operate them due to complex controls. Most users expect a robot to have an intuitive interface that allows them to directly control the platform as well as give them access to some level of autonomous tasks. We aim to introduce this level of intuitive control and autonomous task into teleoperated robotics. This paper proposes a simple sensor-based HMI framework in which a base teleoperated robotic platform is sensorized allowing for basic levels of autonomous tasks as well as provides a foundation for the use of new intuitive interfaces. Multiple forms of HMI’s (Human-Machine Interfaces) are presented and software architecture is proposed. As test cases for the framework, manipulation experiments were performed on a sensorized KUKA YouBot® platform, mobility experiments were performed on a LABO-3 Neptune platform and Nexus 10 tablet was used with multiple users in order to examine the robots ability to adapt to its environment and to its user.

Global-local finite element optimization study to minimize BGA damage under thermal cycling

One of the most critical failure modes in a BGA package is the solder interconnect failure (2nd level). Conventionally, the solder damage is due to the mismatch of coefficient of thermal expansion (CTE) between the various package components and the PCB. It is absolutely critical to identify and minimize the BGA damage under thermal cycling to improve the package reliability. In the past, the critical design parameters have been investigated and ANSYS APDL code has been leveraged with a built in optimization tool for design optimization, thereby improving the solder joint fatigue life [1]. In this work, a multi-level FE model (sub-modeling approach) is implemented in ANSYS Workbench. Multi-variable-design-optimization (MVDO) is performed to minimize BGA fatigue damage. Damage in the BGA is quantified through strain energy density (SED) in the solder joints. The critical material/design parameters that significantly affect the solder joint strain energy density are identified and subsequently optimized to minimize the damage. For enhanced accuracy of the results and to have efficient computational time, sub-modeling technique is leveraged. The analysis is conducted in two steps- 1) “Global model” (coarse) is solved with the full BGA array and the critical joint is identified, 2) the critical joint (detailed far corner joint with fine mesh) is analyzed using sub-modeling.

Coupled computational thermal and mechanical analysis of a single chip flip chip module with low-k dielectric medium

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). While gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnects. Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of Silicon dioxide (k = 3.9) to reduce the capacitive component in the RC delay. Recent research has shown low-k materials to have characteristics such as low mechanical strength and adhesion. In this paper, thermo-mechanical analysis of a single chip flip-chip module (SCM) consisting of a die integrated with low-k dielectric medium, substrate, solder balls, and a printed circuit board (PCB) is performed. The analysis is done in two steps within the ANSYS finite element software to account for thermally induced stresses due to mismatch in thermal expansion coefficient. In the first step, the thermal analysis is carried out to derive the steady state temperature distribution within the package under the imposed power rating. In the second step, the evaluated temperature field is utilized in a coupled thermo-mechanical structural analysis. The developed framework is utilized to study the thermo-mechanical behavior of various low-k dielectrics, wherein the stresses and strain distributions within the chip region are quantified. The analysis has shown no change in the temperature distribution between the base case of Silicon dioxide (SiO2 ) and low-k materials. The maximum equivalent stress in the package, for all the four dielectric cases (SiO2 , polyimide, Hydrogen Silsesquioxane, and Black diamond) is seen in the silicon region of the die and that it does not change with the dielectric materials. However, the maximum equivalent stress in the low-k/metal layers varies with the materials but is always few orders of magnitude less than their corresponding yield strengths. Comparative analysis between Silicon dioxide (SiO2 ) and different low-k materials will help in identifying the weak spots in low-k dielectric when exposed to standard user environments.Copyright

Multi objective optimization of BEoL and fBEOL structure in flip chip package during die attach process

Semiconductor industry has recognized the need to replace traditional Al/SiO2 interconnects with Cu/Low-k interconnects in the mainstream electronics devices following the latters impact on power, RC delay, and cross-talk reduction. However due to lower elastic modulus, strength, and poor adhesion characteristic, reliability of the Cu/Low-k interconnects turns out to be a concern for its integration in the back-end-of-line (BEoL). Flip-chip attachment process (cooling from ~200C to room) can result in critical damage in nano-scale Cu/Low-k interconnects. The objective of this study is to improve the reliability of Cu/Low-k interconnects during die attach reflow process for a specific die to substrate size ratio by varying a group of design parameters such as substrate thickness and solder bump footprint. Preliminary parametric study has shown that the variation in the concerned design variables has a significant effect on the solder bump (fBEoL) and low-k layer damage (BEoL) [1]. However, there is a trade-off between the solder bump and the dielectric damage with bump footprint, thereby arising a need to perform a multi-objective design optimization. A simulation based multi-objective design optimization has been carried out to improve BEoL/fBEoL reliability under reflow loading by minimizing the following objective functions 1) strain energy in the solder bump and 2) peeling stress in dielectric (low-k layers). This work is of immense importance from process integration standpoint. It can provide a quantitative upstream guideline to the process/electrical team on the BEoL/fBEoL damage.

Feasibility of non-linear analysis of the BEoL structure in a flip chip package under thermal shock

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). Though the gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) interconnect delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnect layers in the BEoL (Back-end-of-line). Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of SiO2 (k= 3.9) to reduce the capacitive component in the RC delay. Low-k dielectric materials have characteristics such as low mechanical strength, hardness and adhesion, thereby making it imperative to characterize their thermo-mechanical response. Integration of Cu/low-k interconnects has become a critical reliability issue from the foundrys standpoint as well as package reliability. The thermo-mechanical stresses are induced inside the chip during various fabrication processes, field use, etc. The CTE mismatch between the various components leads to significant warpage and stresses in the metal/dielectric region of the die. In this study, a 3-D multi-level finite element (MLFE) approach has been used to examine the mechanical integrity of the Nano-scale inter-layer-dielectric (ILD) when the package is subjected to thermal shock. Since thickness of each layer in the metal/dielectric region is few orders of magnitude lower than that of the chip/substrate (at least 3 orders) it is almost impossible to analyze it at the global level. Therefore, sub-modeling technique has been leveraged to conduct a relatively accurate estimation of the mechanical behavior of the Cu/low-k region under thermal shock condition. A comparative analysis of the mechanical response of the Cu/low-k region is done for 2 cases - 1) ILD taken as linear material (commonly used industry practice to save computational time) 2) temperature dependent non-linearity of the ILD is implemented and creep and plastic response is captured. The creep model was implemented to represent its realistic mechanical behavior. This study demonstrates the variation in the thermo-mechanical response between the 2 cases thereby addressing the importance of a non-linear analysis for such systems. The developed framework is further utilized to perform a parametric analysis for the number of BEoL layers and to study the effect of underfill properties on the structural integrity of the dielectric layers.