Faizal Arya Samman

Multicast parallel pipeline router architecture for network-on-chip

This paper presents a flexible mesh router architecture using synchronous parallel pipeline worm-switching supporting unicast and multicast services. A very flexible mechanism to manage broadcast-flow to share the communication link in on-chip network is proposed. The proposed mechanism guarantees, that all flits in multicast packets can be accepted in their multiple destination nodes. Our network-on-chip (NoC) is implemented based on modular synthesizable VHDL objects. The architecture is flexible to design new NoC prototypes. Area overhead to update the NoC from unicast to multicast with the same routing algorithm is only about 15%.

Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip

This paper presents the first synthesizable network-on-chip (NoC) based on a mesh topology, which supports adaptive and deadlock-free tree-based multicast routing without virtual channels. The deadlock-free routing algorithms for unicast and multicast packets are the same. Therefore, the routing function gate-level implementation is very efficient. Multicast packets are injected to the network by sending multiple packet headers beforehand. The packet headers contain destination addresses to set up multicast trees connecting a source with multiple destination nodes. An additional locally uniform identification (ID) field is packetized together with flits belonging to the same packet. Therefore, flits of different unicast or multicast packets can be interleaved in the same queue because of the local ID-tags, which are updated and mapped dynamically to support bandwidth scalability of interconnection links. Deadlocks in tree-based multicast routing are handled using a flit-by-flit round arbitration and a fair hold-release tagging mechanism. The effectiveness of the novel mechanism has been experimented under multiple multicast conflicts scenarios, where the experimental results show that all traffic is accepted in-order and lossless in their destination nodes even if adaptive routing functions are used and the sizes of the multicast messages are very long.

New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip

A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.

Networks-on-chip based on dynamic wormhole packet identity mapping management

This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity management. The NoCs are developed based on a VHDL approach and support the design flexibility. The on-chip router uses a wormhole packet switching method with a synchronous parallel pipeline technique. Routing algorithms and dynamic wormhole local packet identity (ID-tag) mapping management are proposed to support a wire sharing methodology and an ID slot division multiplexing technique. At each communication link, flits belonging to the same message have the same local ID-tag, and the ID-tag is updated before the packet enters the next communication link by using an ID-tag mapping management unit. Therefore, flits from different messages can be interleaved, identified, and routed according to their allocated ID slots. Our NoC guarantees in order and lossless message delivery.

Design of an autonomous platform for distributed sensing-actuating systems

A platform for the prototyping of distributed sensing and actuating applications is presented in this paper. By combining a low power FPGA and a System-on-Chip specialized in low power wireless communication, we enabled the development of a large range of smart wireless networks and control systems. Thanks to multiple customization possibilities, the platform can be adapted to specific applications while providing high performance and consuming little energy. We present our approach to design the platform and two application examples showing how it was used in practice in the frame of a research project for adaptronics.

Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip

This paper presents adaptive routing selection strategies suitable for network-on-chip (NoC). The main prototype presented in this paper uses contention information and bandwidth space occupancy to make routing decision at runtime during application execution time. The performance of the NoC router is compared to other NoC routers with queue-length-oriented adaptive routing selection strategies. The evaluation results show that the contention- and bandwidth-aware adaptive routing selection strategies are better than the queue-length-oriented adaptive selection strategies. Messages in the NoC are switched with a wormhole cut-through switching method, where different messages can be interleaved at flit-level in the same communication link without using virtual channels. Hence, the head-of-line blocking problem can be solved effectively and efficiently. The routing control concept and the VLSI microarchitecture of the NoC routers are also presented in this paper.

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip

A VLSI microrchitecture of a network-on-chip (NoC) router with a wormhole cut-through switching method is presented in this paper. The main feature of the NoC router is that, the wormhole messages can be interleaved (cut-through) at flit-level in the same buffer pool and share communication links. Each flit belonging to the same message can track its routing paths correctly because a local identity-tag (ID-tag) is attached on each flit that varies over communication resources to support the wire-sharing message transportation. Flits belonging to the same message will have the same local ID-tag on each communication channel. The concept, on-chip microarchitecture, performance characteristics and interesting transient behaviors of the proposed NoC router that uses the wormhole cut-through switching method are presented in this paper. Routing engine module in the NoC architecture is an exchangeable module and must be designed in accordance with user specification i.e., static or adaptive routing algorithm. For quality of service purpose, inter-switch data transfers are controlled by using link-level overflow control to avoid drops of data.

Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method

Networks-on-chip (NoC) router microarchitectures in mesh standard architectures and a mesh planar architecture with a dual-vertical-line are presented in this paper. Both NoC microarchitectures support a deadlock-free static and efficient adaptive tree-based multicast routing method. Multicast packets are routed and scheduled in the NoC by using a flexible multiplexing technique with wormhole switching. The flexibility of the proposed multicast routing method is based on a locally organized packet identity (ID-tag) attached to every flit. This concept allows different packets to be interleaved at flit-level in a single buffer pool on the same link. Furthermore, a pheromone tracking strategy is proposed in this paper in order to reduce communication energy in the adaptive tree-based multicast routing method. The strategy is used to perform efficient spanning trees for the adaptive tree-based multicast routing that are made at runtime during application execution time.

Adaptive wireless sensor networks powered by hybrid energy harvesting for environmental monitoring

Due to the cost-effective nature and deployment flexibility of wireless sensor network (WSN), it has been extensively used in many real world applications. Sensor nodes are relatively inexpensive and capable of data processing and wireless communication with some level of intelligence, they play a key role in real world applications. Precision irrigation in agriculture is a key application of wireless sensor network. Typically, a sensor node is powered by its on-board battery source. This limitation fully or partially contributes to causing many problems in the network such as the loss of connectivity of a sensor node known as orphaned-node. Moreover, available number of sensor types in a sensor node is typically limited and it requires a significant modification in hardware and software interfaces to extend the number of sensor types. In this paper, we propose an adaptive sensor node system combining a flexible hardware prototype and innovative energy harvesting techniques to optimise the performance of the network operating in a large farming environment.

Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system.