Falko Guderian

Entering the path towards terabit/s wireless links

Wireless communications has been a hot area of technology advancement for the past two decades. As long as memory sizes increase, the demand for higher data rates of communications increases on the same scale. This means that one must understand todays high-end 10 Gbit/s wireless technology to get prepared for 100 Gbit/s and 1 Tbit/s data rates of tomorrow. This paper presents key boundary conditions learned by understanding leading edge wireless links of today to prepare for the Tbit/s technology of the year 2020.

Fair rate packet arbitration in Network-on-Chip

This paper proposes two new arbitration techniques to enable fair link bandwidth allocation. One technique is a weighted round-robin scheme with weights based on the number of contending flows at the input port. The second technique is an age-based scheme with probabilistic arbitration where the traversed packet distance approximates age. Opposed to existing work, both schemes reach almost absolute fairness of link bandwidth allocation and simplify calculation of arbitration metrics.

Towards a wireless medical smart card

Wireless data transmission has become an integral part of modern society and plays an increasingly important role in health care. Technology scaling is continuously increasing wireless data rates, thus allowing for more flexible high-speed interfaces, e.g., between medical imaging equipment and mass storage devices. However, one issue remains: The power consumption of high-speed wireless transceivers and non-volatile memory grows with the data rate. This prevents from innovations using these high-speed wireless interfaces in ultra-low power (or even energy-passive) medical equipment that can be used by patients without a heavy power source. Clear efforts are required to close this gap, i.e., to provide high-speed wireless solutions with reduced energy consumption per transmitted bit. As a very example, this work presents the concept of a wireless medical smart card that combines near field communication for authentication and low-speed signaling together with a 60GHz interface for fast wireless memory access in a single patient-owned ID card. The basic architecture, functionality and prospects of the concept are discussed. A power budget is calculated based on state-of-the-art technologies. To put the concept into practice, some necessary developments for a reduction of the power consumption are outlined.

Dimensioning the heterogeneous multicluster architecture via parallelism analysis and evolutionary computing

In the near future, embedded systems containing hundreds of processing elements running multiple concurrent applications will become a reality. The heterogeneous multicluster architecture enables to cope with the challenging hardware/software requirements presented by such systems. This paper shows principles and optimization of multicluster dimensioning aiming at an appropriate distribution of applications onto clusters containing different types of processing elements. The approach represents an initial exploration phase efficiently finding a suitable multicluster configuration in the large design space. Hence, results should be further refined by more accurate but less time-efficient simulation-based techniques. As the starting point, a parallelism value matrix is analytically extracted describing application mappings independently on the architecture and scheduling. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) approach solving the dimensioning problem are introduced and compared. Both solutions use the parallelism value matrix as input. Scalability results show that the GA generates results faster and with a satisfactory quality relative to the found MILP solutions. Finally, the dimensioning approach is demonstrated for a realistic benchmark scenario.

Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing

In this paper, we address the problem of an efficient mapping of intellectual property (IP) cores onto a multiprocessor system-on-chip (MPSoC). The MPSoC is statically scalable in terms of number of IP cores and an 1-ary n-mesh network-on-chip (NoC). The approach places more affine IP cores closer to each other and affinity is based on an amount of exchanged communication and administration data. Assuming ideal network conditions, accounting for execution latency, separate affinity value matrices for communication and administration are extracted from the application mappings. Aiming at better system performance, the goal is to find a reasonable tradeoff between communication and administration affinity. Hence, both matrices are merged into a single affinity value matrix based on linear weighting. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) solution use the weighted affinity value matrix to efficiently map IP cores onto a NoC. A scalability analysis shows that the GA generates results faster and with a satisfactory quality relative to the found MILP solutions. Realistic benchmark results demonstrate that a tradeoff between administration and communication affinity significantly reduces administration latency improving application performance. As network size and system adaptability increase, the growing influence of administration becomes more evident.