Fang Luo

Common-mode noise comparison study for lateral wire-bonded and vertically integrated power modules

This paper investigates the power module design for better common-mode (CM) noise performance. A high frequency full-bridge diode rectifier is studied as an example. For this circuit, a comprehensive parametric study and a proposed CM equivalent model are first presented to identify the most influential factors in CM noise generation and mitigation. It is shown that proper parasitic value and parasitics symmetry can improve the CM noise performance. A vertical module and a traditional wire-bonded lateral module are compared. The vertical module has smaller ac side CM parasitic capacitances, smaller ac side stray inductances and larger dc side CM parasitic capacitances, which are all favorable towards mitigating CM noise. Both modules are prototyped for verification, and their module parasitics are extracted using finite element method (FEM). A simulation case study shows that with the vertical diode module, over 30 dB CM noise reduction can be achieved below 10 MHz, under 7.4% unbalance between the ac side CM parasitic capacitances. Experimental results are presented to verify the simulation and analysis. It is also shown in thermal simulation that the vertical module exhibits at least 30% reduction on the thermal impedance.

Comprehensive evaluation of a silicon-WBG hybrid switch

In this paper, a hybrid switch (HyS) consisting of a large silicon (Si) IGBT die in parallel with a small wide bandgap (WBG) die is proposed for generic power conversion drives. This HyS produces an inherent better conduction performance compared to the Si IGBT and WBG. A gate control option is recommended for minimum switching losses and switching frequency as high as 78 kHz can be achieved in HyS based converters. A parametric study was performed on the influence of the parasitic interconnect inductances within the switch. The recommended gate control option can be used for an inductance unbalance of less than 10 nH within the IGBT and WBG cell. For higher inductance an alternative gate control strategy is proposed for reduced switching losses. Experimental results show the benefits of the HyS. An algorithm is proposed for the optimum Si/WBG die current ratio. A case study involving transient thermal analysis is performed to show that a Si/WBG current ratio as high as 6:1 can be realized while ensuring the integrity of both dies.

High density EMI mitigation solution using active approaches

Passive EMI filters occupy significant volume in a power converter. This work involves the study of utilizing Active EMI Filters (AEF) and Hybrid EMI Filters (HEF) to reduce the volume of passive filters. The DUT under consideration is a 30 W AC-DC converter. Since the power level less than 65 W it does not have a PFC stage. In this work, noise sensing is carried out using voltage sensing methodology. The applicability of the sensing method to sense noise and its relation to the maximum possible attenuation is studied. Noise sensing networks comprising the high voltage capacitors and high pass filter networks to are designed for sensing noise on AC and Dc side. For noise cancellation, feedback control scheme with both voltage and current cancellation topologies are employed separately. The possible value reduction of passive components for both topologies of AEF are identified.

Optimal submodule capacitor sizing for modular multilevel converters with common mode voltage injection and circulating current control

Modular multilevel converters (MMCs), with the filter-less and transformer-less features, are considered as a promising topology for high-efficiency medium voltage (MV) high voltage (HV) drive systems. However, at low frequencies (< 30 Hz), a large current ripple flowing through the capacitors of each submodule will cause significant capacitor voltage fluctuation. This paper proposes an optimal submodule capacitor selection based on the common mode voltage injection. The proposed sizing model includes two functions: a) accurately estimating the capacitor voltage ripple based on the drive system parameters; and b) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and hardware-in-the-loop (HIL) test results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

Comprehensive evaluation of interleaved zero current switching inverter against interleaved hard switching inverters in terms of efficiency, power density and EMI spectrum

This paper presents a comparison between two types of interleaved voltage source inverter (VSI) topologies, an Interleaved Zero-Current-Transition Inverter (IZCTI) and an In-terleaved Hard-Switching Inverter (IHSI). Zero current transition in IZCTI is presented in switching trajectory and compared with hard switching trajectory to evaluate the switching loss reduction. Then four pulse test is devised to evaluate the switching loss in zero current transition, and experimental result is shown. As for IZCTI, an inter-phase inductance selection principle is proposed based on resonating circuit. Moreover, a scaled-down version 1 kW single phase inverter prototypes of both topologies are built to demonstrate the validity of topologies and their technique. A comprehensive comparison between IZCTI and IHSI is presented in terms of efficiency, power density and EMI performance.

Impact of cable and motor loads on wide bandgap device switching and reflected wave phenomenon in motor drives

In inverter based motor drives, the fast switching speeds of the power devices result in over-voltage at the motor end. Corresponding to these over-voltages at the motor end, there are over-currents at the inverter end. While the over-voltage increases stress on motor and cable insulation, the load and the cable parasitics increases the switching loss of the power devices. These effects are more pronounced in converters using Wide Bandgap (WBG) devices because of the their faster switching speed. Previous works have only studied either over-voltages or currents in converters with low source impedance. In this paper, the effect of inductive source impedance on the Reflected Wave Phenomenon (RWP) is studied. The impact of different filter topologies (used to mitigate the RWP) on the switching losses of the devices. Also, the effect of the cable parasitic including the ground and shield wires are studied here. Experiments are carried out to identify losses in different filter topologies, RWP, switching losses of devices and dv/dt at the load.

An improved wire-bonded power module with double-end sourced structure

This paper proposes a wire-bonded design with a unique double-end sourced structure for multi-chip paralleled SiC power modules. The proposed design achieved a reduced power-loop inductance of 7.2 nH, while inheriting the advantages of the conventional wire-bond technology. More importantly, the symmetrical structure of the proposed design brought consistent performances to the paralleled devices. A 1200 V, 60 A SiC MOSFET half-bridge module (3 devices in parallel) was fabricated and tested for verification. It demonstrated suppressed voltage overshoot and improved current-sharing among the devices. In addition, the proposed layout exhibited lower radiation noises, which will cause less interference to the sensitive electronic devices. A converter level design is also presented to accommodate this unique module structure.

A double-end sourced multi-chip improved wire-bonded SiC MOSFET power module design

This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) power modules. The new structure adopts two pairs of DC bus-bars to source the power module from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved a minimized power-loop inductance of 7.2 nH. In addition, the design improved current sharing among the paralleled devices. A 1200 V, 60 A SiC metal-oxide-semiconductor field-effecttransistor (MOSFET) half-bridge module (3 devices in parallel) is fabricated and tested for verification. Improved performances are observed in both switching and continuous operation. A converter level design is also presented to accommodate this unique module structure.

A high power-density three-phase inverter adopting the double-end sourced power module layout

This paper proposes a double-end sourced layout for wire-bonded multi-chip paralleled silicon carbide power modules. The simulation results demonstrate suppressed voltage-overshoot and improved current-sharing with the proposed layout, as well as reduced total switching losses and a more even loss-distribution among paralleling devices. Power modules were fabricated in the lab, a double-pulse test and continuous power test were conducted, whose outcomes verified the simulation results. Furthermore, this paper investigates and compares the thermal management on the proposed layout and the conventional baseline layout. It proves that the proposed structure has a smaller footprint on the heatsink under the same thermal requirements. Finally, a high power-density three-phase inverter that adopts the proposed structure was designed and tested.