Fang Lv

Articulation points guided redundancy elimination for betweenness centrality

Betweenness centrality (BC) is an important metrics in graph analysis which indicates critical vertices in large-scale networks based on shortest path enumeration. Typically, a BC algorithm constructs a shortest-path DAG for each vertex to calculate its BC score. However, for emerging real-world graphs, even the state-of-the-art BC algorithm will introduce a number of redundancies, as suggested by the existence of articulation points. Articulation points imply some common sub-DAGs in the DAGs for different vertices, but existing algorithms do not leverage such information and miss the optimization opportunity. We propose a redundancy elimination approach, which identifies the common sub-DAGs shared between the DAGs for different vertices. Our approach leverages the articulation points and reuses the results of the common sub-DAGs in calculating the BC scores, which eliminates redundant computations. We implemented the approach as an algorithm with two-level parallelism and evaluated it on a multicore platform. Compared to the state-of-the-art implementation using shared memory, our approach achieves an average speedup of 4.6x across a variety of real-world graphs, with the traversal rates up to 45 ~ 2400 MTEPS (Millions of Traversed Edges per Second).

Efficient Management for Hybrid Memory in Managed Language Runtime

Hybrid memory, which leverages the benefits of traditional DRAM and emerging memory technologies, is a promising alternative for future main memory design. However popular management policies through memory-access recording and page migration may invoke non-trivial overhead in execution time and hardware space. Nowadays, managed language applications are increasingly dominant in every kind of platform. Managed runtimes provide services for automatic memory management. So it is important to adapt them for the underlying hybrid memory.

Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

Efficiency of batch processing is becoming increasingly important for many modern commercial service centers, e.g., clusters and cloud computing datacenters. However, periodical resource contentions have become the major performance obstacles for concurrently running applications on mainstream CMP servers. I/O contention is such a kind of obstacle, which may impede both the co-running performance of batch jobs and the system throughput seriously. In this paper, a dynamic I/O-aware scheduling algorithm is proposed to lower the impacts of I/O contention and to enhance the co-running performance in batch processing. We set up our environment on an 8-socket, 64-core server in Dawning Linux Cluster. Fifteen workloads ranging from 8 jobs to 256 jobs are evaluated. Our experimental results show significant improvements on the throughputs of the workloads, which range from 7% to 431%. Meanwhile, noticeable improvements on the slowdown of workloads and the average runtime for each job can be achieved. These results show that a well-tuned dynamic I/O-aware scheduler is beneficial for batch-mode services. It can also enhance the resource utilization via throughput improvement on modern service platforms.

Lazygraph: lazy data coherency for replicas in distributed graph-parallel computation

Replicas 1 of a vertex play an important role in existing distributed graph processing systems which make a single vertex to be parallel processed by multiple machines and access remote neighbors locally without any remote access. However, replicas of vertices introduce data coherency problem. Existing distributed graph systems treat replicas of a vertex v as an atomic and indivisible vertex, and use an eager data coherency approach to guarantee replicas atomicity. In eager data coherency approach, any changes to vertex data must be immediately communicated to all replicas of v, thus leading to frequent global synchronizations and communications. In this paper, we propose a lazy data coherency approach, called LazyAsync, which treats replicas of a vertex as independent vertices and maintains the data coherency by computations, rather than communications in existing eager approach. Our approach automatically selects some data coherency points from the graph algorithm, and maintains all replicas to share the same global view only at such points, which means the replicas are enabled to maintain different local views between any two adjacent data coherency points. Based on PowerGraph, we develop a distributed graph processing system LazyGraph to implement the LazyAsync approach and exploit graph-aware optimizations. On a 48-node EC2-like cluster, LazyGraph outperforms PowerGraph on four widely used graph algorithms across a variety of real-world graphs, with a speedup ranging from 1.25x to 10.69x.

NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture

The high density, low power consumption non-volatile memory (NVM) provides a promising DRAM alternative for the in-memory big-data processing applications, e.g., Spark, It is significant to simulate the behaviors when NVMs are deployed into the area of big-data processing before their widespread use in market. However, existing simulation approaches are not applicable for big-data processing due to two reasons. First, some approaches require complicated hardware and/or OS supports. Second, cycle-level or function-level simulations are too time-consuming to simulate the whole software stack of big-data processing. Therefore, the complexity and expensive time cost in NVM simulation have dramatically dragged down the integrated research of big data with NVM. This paper proposes a fast and reconfigurable simulation method, called NVM Streaker, which does not need complex hardware or OS supports. It simulates NVM access costs using disturbed DRAM accesses and commonly configurable hardware parameters. It is fast since we use DRAM accesses and change its access costs to simulate NVM access costs, thus enabling to simulate the whole software stack to run Spark applications. It is reconfigurable since we enable users to configure the disturbed memory access costs, in order to simulate different NVM access costs. The experimental results show that we can simulate Spark applications with almost negligible cost and high efficiency.

Irradiance and Temperature Dependence Characterization of Vacuum Glass BIPV Modules

This paper gives the electrical performance characteristics of vacuum glass building integrated photovoltaic (BIPV) modules used as roofing system of building markets. Considering materials and structures are totally different from that of traditional PV module. The optimum power rating condition need be evaluated and analyzed to obtain irradiance and temperature dependence. A temperature and irradiance matrix of performance parameters of a BIPV module is given to predict the energy produced by this BIPV product. To define a suitable standard test condition of vacuum glass BIPV module, the electrical performances under different incident angle and sunlight spectrum are also measured and discussed in this paper.