Farhad Mehdipour

An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems

Abstract Lack of appropriate compilers for generating configurations and their scheduling is one of the main challenges in the development of reconfigurable computing systems. In this paper, a new iterative design flow for reconfigurable computing systems is proposed that integrates the synthesis and physical design phases to perform a static compilation process. We propose a new temporal partitioning algorithm for partitioning and scheduling, which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. In addition, we perform an incremental physical design process based on similar configurations produced in the partitioning stage. To validate the effectiveness of our methodology and algorithms, we developed a framework according to the proposed methodology.

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework

In reconfigurable systems, reconfiguration latency is a very important factor which impact the system performance. In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. A temporal partitioning algorithm is proposed which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. This algorithm attempts to find similar single or pair of operations between subsequent partitions. Considering similar pairs instead of single nodes brings about less complexity for routing process. By using this technique, smaller reconfiguration bit-stream is obtained, which directly decreases the reconfiguration overhead time at the run-time. A complementary algorithm attempts to increase the similarity of subsequent partitions by searching for similar pairs and using a technique called dummy node insertion. An incremental physical design process based on similar configurations produced in the partitioning stage improves the metrics over iterations.

An integrated temporal partitioning and mapping framework for handling custom instructions on a reconfigurable functional unit

Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches for CI generation with respect to the RFU constraints to improve speedup of the extensible processor. First, our proposed RFU architecture for an adaptive dynamic extensible processor called AMBER is described. Then, an integrated temporal partitioning and mapping framework is presented to partition and map the CIs on the RFU. In this framework, a mapping aware temporal partitioning algorithm is used to generate CIs which are mappable on the RFU. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. In addition, a mapping algorithm is presented which supports CIs with critical path length more than the RFU depth.

A survey on big data processing infrastructure: evolving role of FPGA

In todays commercial world, information is becoming a major economic resource thus leading to a statement - information is wealth. It is a technical challenge for computer systems in managing and analysing the large volumes of data coming from a variety of resources continuously over a period. Experts are in a mood of moving towards alternative hardware platforms for achieving high-speed data processing and analysis especially for streaming applications. In this paper: a) existing trends in big data processing and the necessary systems involved are studied by performing a survey on available platforms; b) recommended features and suitable hardware systems are proposed based on the operations involved in the processing. Investigation shows that, in combination with CPU and along with GPU, FPGA is a possible alternative. It can be a part of the heterogeneous platform featuring parallelism, pipelining and high performance for the operations involved in big data processing.

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problems of this approach are immense cost and long time of designing. To address these issues, an adaptive extensible processor was proposed in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units with the capability of conditional execution. Unlike previous proposed CIs, it can include multiple exits. Experimental results show that multi-exit CIs enhance the performance by 46% in average compared to CIs limited to one basic block. A maximum speedup of 2.89 compared to a 4-issue in-order RISC processor, and a speedup of 1.66 in average, was achieved on MiBench benchmark suite

Implementation of cellular learning automata on reconfigurable computing systems

Reconfigurable computing systems (RCS) use the flexibility of programmable devices and the speed of hardware to implement high performance systems. Implementation of RCS is normally made by means of programmable devices, such as FPGAs. On the other hand, recently, cellular learning automata (CLA) have been proposed as a combination of conventional cellular automaton and learning automaton. Software simulation of CLA has shown it to be successful for solving some hard problems. However, the process on conventional computers is slow. To overcome this problem, we implemented CLA in hardware. In addition, for some applications which necessitate run time changes for parameters, the ability of run-time reconfiguration (RTR) in hardware is a solution. In this paper, the design and implementation of CLA on a reconfigurable system are presented. Experimental results show considerable speedup gain of RCS version over the software version. Independence on CLA dimensions is another benefit of reconfigurable hardware implementation of CLA. In other words, by increasing the dimensions of CLA, the time needed for running reconfigurable CLA implemented on hardware remains constant.

Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems

For running subsequent configurations in a reconfigurable computing system intermediate data must transfer between them. Reducing memory usage overhead can result in reduction in the array size and the number of input/output pins. In this paper, a new iterative design flow is proposed which integrates the synthesis and physical design aspects for performing a static compilation process. A new temporal partitioning algorithm for partitioning and scheduling is proposed, which tries to increase similarity of subsequent configurations in such a way that the reconfiguration time on a partially reconfigurable hardware decreases. In addition, we perform an iterative physical design process based on similar configurations produced in the previous stage. A modified algorithm improves our prior temporal partitioning algorithm, which usually had large overhead of memory usage and the number of input/output pins. This new approach performs partitioning in depth and tries to minimize the memory and 10 requirements.

A reconfigurable architecture for implementing multiple cipher algorithms

Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. In this paper, we implemented multiple cryptographic algorithms, namely DES, LOKI, DESX, Biham-DES, and S/sup n/DES on a reconfigurable hardware. Our implementation results in a high flexibility and similar ciphering rate in compare with the previous implementations reported in FPGAs.

A high performance reconfigurable implementation of DES-like algorithms

Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of FPGAs. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.