Fathi Abugchem

A Note on the Suboptimality of Nonpreemptive Real-time Scheduling

In this letter, processor speedup analysis is used to strengthen recent results regarding the suboptimality of uniprocessor nonpreemptive earliest deadline first (npEDF) scheduling. The suboptimality of npEDF is defined as the minimum amount of increase in the processor speed that is needed to guarantee the npEDF schedulability of any feasible task set. We show that any preemptively schedulable task set that is not schedulable by npEDF will become schedulable on a processor speeded up by a factor of not more than one plus the value of the largest execution requirement divided by the shortest relative deadline of any task. This reduces the pessimism compared to the best previous bound by factor of at least two. In addition, for the case of nonpreemptive Fixed Priority scheduling, we also show that twice this speedup bound is enough to guarantee the schedulability of any feasible task set.

A hybrid EDF algorithm for implementing resource-constrained real-time control applications

It is well known that the performance of real-time control applications can be seriously degraded by sampling and actuation jitters and delays. This paper describes a simple hybrid-EDF algorithm which may help to ameliorate some of these problems in resource-constrained embedded systems in which the use of simplified and non-preemptive schedulers is required. The algorithm supports a single preemptive time-critical sampling and actuation task, whilst the remaining tasks are executed non-preemptively and have implicit deadlines. The paper develops an efficient schedulability analysis technique for this framework; analysis and an example are given to illustrate the improvement in efficiency over related techniques.

An experimental HIL study on the jitter sensitivity of an adaptive control system

It has been widely accepted that real-time implementations of feedback control systems can be susceptible to timing jitters which may be caused by the underlying real-time and/or embedded implementation architecture. Previous experimental studies aimed at quantifying the levels of degradation that may be observed have mainly concentrated upon relatively simple fixed-gain feedback control schemes (e.g. PID) and time-invariant plant. Although some degradation has been observed, most systems have been shown to be surprisingly robust unless driven to extreme limits. In this paper, we study the jitter sensitivity of a real-time embedded implementation of a digital parameter-adaptive control system. The purpose of the study was two-fold; primarily, to obtain empirical data related to jitter sensitivity (as measured by a quadratic performance metric), and secondarily to explore the potential impact of the underlying scheduler choice on system behavior. The findings indicate that the adaptive controller was heavily influenced by sampling jitter, and that the choice of task scheduler had a role to play.

Application level compensation for burst errors in wireless control networks

The use of wireless communications in real-time control applications poses several severe problems related to the comparatively low reliability of the communication channels. This paper is concerned with application-level strategies for ameliorating the effects of packet losses and burst errors in sampled-data control systems implemented via one or more wireless links. In particular, the paper develops an adaptive/predictive compensator that reconstructs the best estimates (in a least squares sense) of a sequence of one or more missing process data packets. An embedded implementation of the proposed technique is applied to a case study, and it is shown that the proposed techniques outperform existing methods in a control system experiencing artificially induced burst errors, whilst also exhibiting acceptably low overheads.

A test facility for experimental HIL analysis of industrial embedded control systems

It is well known that the performance of real-time control applications can be affected by many factors, including the choice (and configuration) of the hardware platform and task scheduling algorithm. This paper presents a real-time hardware-in-the-loop simulation tool that simultaneously integrates concepts from control and real-time computing to allow further investigation into these links. It allows the experimental prototyping and analysis of real-time control systems on real hardware - but within a simulated plant environment -and thus allows the potential impacts of hardware and software architecture on control performance and dependability to be evaluated. The structure of the proposed tool is described, along with a preliminary experiment that has been performed to illustrate some of the test facility capabilities.

An embedded prototype of a residential smart appliance scheduling system

Demand Response (DR) is seen as one of the key enabling factors in the emerging smart grid. DR takes many forms, including residential smart appliance scheduling. Scheduling algorithms capable of achieving near-minimum cost solutions with low computational overhead are required in order to autonomously respond to varying utility pricing signals. In this paper, the focus is upon an embedded software prototype implementation of a residential load scheduling system. It describes the implementation and testing of a heuristic algorithm for household energy management on a small embedded processor. The performance of the prototype implementation is validated against previously reported experiments and simulations. Test results indicate that the heuristic is efficient enough to be co-located on a small smart meter with limited memory and processing power without any difficulties, helping to open the way for practical consumer demand response.

Jitter Sensitivity of A Self-Tuning Input-Constrained Predictive Controller

In this paper, the jitter sensitivity of a real-time embedded implementation of a self-tuning generalized predictive control algorithm will be experimentally investigated using a hardware-in-the-loop testing technique. The aim of the study was to explore the potential impacts of slew rate limits of the input of the controlled system on the performance of the controller when jitter is present. The paper also examines the effects of different preemption levels of the underlying earliest deadline first scheduler on the performance of the control system.