Fazel Sharifi

Two novel ultra high speed carbon nanotube Full-Adder cells

In this paper two ultra high speed carbon nanotube Full-Adder cells are presented. First design uses two transistors, two resistors and seven capacitors and the second one uses four transistors and seven capacitors. The first design is faster and the second one consumes less power. Simulation results illustrate significant improvement in terms of speed and Power-Delay Product (PDP).

Robust and energy-efficient carbon nanotube FET-based MVL gates

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs.

Five New MVL Current Mode Differential Absolute Value Circuits Based on Carbon Nano-tube Field Effect Transistors (CNTFETs)

Carbon Nano-Tube Field Effect Transistors (CNTFETs) are being widely studied as possible successors to silicon MOSFETs. Using current mode has many advantages such as performing sum operation by means of a simple wired connection. Also, direction of the current can be used to exhibit the sign of digits. It is expected that the advantages of current mode approaches will become even more important with increased speed requirements and decreased supply voltage. In this paper, we present five new circuit designs for differential absolute value in current mode logic which have been simulated by CNTFET model. The considered base current for this model is 2 µA and supply voltage is 0.9 V. In all of our designs we used N-type CNTFET current mirrors which operate as truncated difference circuits. The operation of Differential Absolute Value circuit calculates the difference between two input currents and our circuit designs are operate in 8 logic levels.

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.

Design and analysis of carbon nanotube FET based quaternary full adders

CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

Ultra-low-power carbon nanotube FET-based quaternary logic gates

ABSTRACT This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.

High-performance ternary logic gates for nanoelectronics

This paper presents high-performance ternary buffer STB, minimum STMin and maximum STMax circuits using carbon nanotube field effect transistors CNTFETs. Multiple valued logic MVL has been introduced to overcome the complexity and interconnection problems of the binary integrated circuits. In addition, outstanding properties of CNTFETs such as possibility of adopting the desired threshold voltage make them very appropriate for voltage mode MVL circuits design. All circuits are examined in different conditions using Synopsys HSPICE simulator at 32 nm feature size. Power-delay product PDP of the proposed designs are lower than the latest presented ternary circuits about 33%, 33% and 64%, respectively.

High Performance CNFET-based Ternary Full Adders

ABSTRACT This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature, and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET-based ternary full adders.

Design of quaternary 4-2 and 5-2 compressors for nanotechnology

Recently, Multiple Valued Logic (MVL) has attracted attention, because it reduces the area and complexity of circuits when compared to binary logic. Carbon nanotube field effect transistors (CNFET) are a good candidate for implementing MVL logic circuits, since determining the threshold voltage value of CNFET is easily achievable by changing the diameter of the nanotubes which are placed under the transistor gate. In this paper, quaternary CNFET based 4-2 and 5-2 compressor cells have been proposed. The proposed cell designs were investigated using HSPICE simulator with the standard 32nm CNFET technology under different operational conditions such as different temperatures, different load capacitances, and different supply voltages. Also the sensitivity to process variations and noise immunity of the proposed designs have been investigated. The proposed quaternary logic designs reduce the delay of the multi operand addition of arithmetic circuits by eliminating the carry propagation overhead.

On the design of quaternary arithmetic logic unit based on CNTFETs

ABSTRACT A new approach for designing a quaternary arithmetic logic unit (ALU) based on carbon nanotube field-effect transistors (CNTFETs) is presented in this paper. The proposed design performs basic arithmetic and logic functions and is extendable to perform additional functions (both arithmetic and logic functions). Efficient circuit-level optimisation techniques such as data gating are used to reduce the power consumption and enhance the performance of the proposed design. In addition, the unique properties of CNTFETs such as adjusting the threshold voltages of CNTFETs by tuning the CNTs diameters are utilised for designing a quaternary ALU. The proposed design is simulated and examined in different conditions and in the presence of major process variations using the Synopsys HSPICE simulator with Stanford 32nm CNTFET technology.