Fei Qiao

The research on dispatching rule for improving on-time delivery for semiconductor wafer fab

Semiconductor wafer fab cries for really dynamic dispatching approach, due to its high uncertainty, re-entrance and large-scale. A dispatching rule for improving on-time delivery for semiconductor wafer fab (ODDR) is proposed, which considers the dispatching of bottleneck machines, not-bottleneck machines, batching machines and hot lots. As a result, it can distinctly improve on-time delivery without decreasing the throughput and increasing the cycle time. Finally, a simplistic model, but with essential characteristics of semiconductor wafer fab, is used to compare ODDR with FIFO, EDD and CR. It can be seen from the experimental results that ODDR is prior to FIFO, EDD and CR on throughput, cycle time and on-time delivery with better performance, especially for on-time delivery.

ACO-based scheduling for a single Batch Processing Machine in semiconductor manufacturing

This research is motivated by the scheduling problem in the diffusion and oxidation operations of semiconductor wafer fabrication facilities (fabs), where one machine is modeled as a single batch processing machine. The objective is to minimize the total weighted tardiness (TWT) on a single batch processing machine (BPM) with incompatible lot families and dynamic lot arrivals, with consideration on the sequence-dependent setup time. Since the problem is NP-hard, ant colony optimization (ACO) is used to achieve a satisfactory solution in a reasonable computation time. Extensive experiments have been implemented to validate and verify the proposed method. It is shown by the simulation results that the proposed method is superior to the common apparent tardiness cost- batched apparent tardiness cost (ATC-BATC) rule with smaller TWT and makespan, especially TWT that is improved by 40.07% on average.

The impact of the qual-run requirements of APC on the scheduling performance in semiconductor manufacturing

This research is motivated by the qual-run requirements of Advance Process Control(APC) opposite setups of scheduling in semiconductor manufacturing. The objective is to analyze the impact of the qual-run requirements of APC on the scheduling performance (e.g. the Total Weighted Tardiness (TWT) and makespan)with a number of experiments. Taking parallel machines for example, we propose an Ant Colony Optimization (ACO) algorithm to reach a satisfactory solution in a reasonable computation time under both scenarios of with or without consideration on the qual-run requirements of APC to do the evaluation. It is shown by the simulation results that the qual-run requirements of APC have important impact on the scheduling performance. The total average improvements on TWT and makespan are 15.38% and 10.21%, respectively, of the ACO solution with consideration on the qual-run requirements of APC comparing to the ACO solution without consideration on the qual-run requirements of APC. In addition, the more scheduled lots and more recipes on one machine, the stronger the impact of the qual-run requirements of APC is.

Agent-based dynamic scheduling for semiconductor wafer fab

Semiconductor wafer fab is considered as the third kind of production system, differentiated with job shop and flow shop. It has its own scheduling and control characteristics, such as re-entrance, large-scale, mix processing model and unbalanced production facilities. To solve scheduling problem of semiconductor wafer fab, an agent-based scheduling approach for semiconductor wafer fab is proposed. Firstly, an agent-based scheduling model, which integrates release control, dispatching and machine maintenance scheduling, is presented. Secondly, negotiation protocol between agents, extended contract net protocol (ECNP), is given. Thirdly, scheduling algorithms for decision making of agents are offered. Finally, a simple model, but with essential characters of semiconductor wafer fabrication, is used to demonstrate how to use the proposed agent-based scheduling approach.

A new compound priority control strategy in semiconductor wafer fabrication

Control problems in semiconductor manufacturing include lot release and scheduling, while they were investigated separately. A new compound priority control strategy, CPC, is discussed, which takes both the lot release strategy and the scheduling strategy into account. According to the compound priorities of jobs that compete for processing, the CPC strategy can determine which lot(s) is/are processed when the machine is available, and determine when the new lot(s) is/are released into the wafer fab. The CPC strategy can even halt the non-bottleneck machines to prevent overstock of WIP before the bottleneck machines. Simulation results indicate that the CPC strategy has higher performance in reducing the cycle time and its standard deviation, and decreasing the WIP inventory.

Cloud manufacturing application in semiconductor industry

This paper aims to shed some light on how the concept of cloud manufacturing has been applied to the semiconductor manufacturing operations. It starts with describing the challenges to the semiconductor manufacturing due to evolving of outsourcing business model in global context, then discusses the different forms of cloud manufacturing and proposes the semiconductor industry oriented architecture for cloud manufacturing. Serus is used as a case study to share how the cloud manufacturing has created the values for the customer and its outsourced suppliers in the semiconductor industry.

Improving wafer fabrication performance by Hierarchical colored timed Petri-net and SA - based approach

The paper describes an approach to scheduling for semiconductor wafer fabrication. In order to effectively analyze of control for semiconductor wafer fabrication, a Hierarchical colored timed Petri net (HCTPN) modeling technology based on the comprehensive analysis of the semiconductor manufacturing process was proposed. Due to the wide acceptance of priority rules in the wafer fabrication, we proposed a simulated annealing (SA) to search for the optimal combination of a number of priority rules in the HCTPN models. Computational results are presented that our approach constantly generates better solutions compared to those obtained by commonly- used dispatching rules.

Parallel simulation-based optimization on scheduling of a semiconductor manufacturing system

As an important and challenging problem, the scheduling of semiconductor manufacturing is a hot topic in both engineering and academic fields. Its purpose is to satisfy production constraints on both production process and resources, as well as optimizing some performance indexes like cycle-time, movement, etc. However, due to its complexities, it is hard to describe the scheduling process with a mathematical model, or to use conventional methods to optimize its scheduling problem. A Simulation approach is proposed to optimize the scheduling of a semiconductor manufacturing system, i.e. a simulation-based optimization (SBO) approach. Because the high computational cost of SBO approach could hinder its application in the real production line, a parallel/distributed architecture is discussed to improve its efficiency. Using genetic algorithm (GA) as an optimization algorithm, the proposed parallel-SBO based scheduling approach for semiconductor manufacturing system is tested for its feasibility and effectiveness.

An Algorithm of Production Scheduling for Pulling Production Systems with Resource Constraints

For the production scheduling of bottleneck of pulling production systems with resource constraints, a time-margin-based heuristic algorithm (TMBHA) is proposed to realize the optimization of facility utilization and intermediate inventory based on discrete-event simulation. Compared with manual scheduling and genetic algorithm (GA), the result shows TMBHA is effective in the aspect of efficiency and computation time.

Scheduling Semiconductor Wafer Fabrication with Optimization of Multiple objectives

CPC is a compound priority control strategy used for scheduling semiconductor wafer fabrication. The compound priority of wafers is calculated according to their current processing step, to the amount of wafers waiting for processing in current step buffer, in upstream step buffer, and in downstream step buffer. Wafers with the highest compound priority are dispatched to certain machine to be processed. Compared to common used scheduling strategies, CPC strategy exhibits high performance in reducing total amount of WIP, decreasing cycle time and its standard deviation, and increasing the throughput rate