Feifan Wang

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Ultracompact all-optical full-adder and half-adder based on nonlinear plasmonic nanocavities

Abstract Ultracompact chip-integrated all-optical half- and full-adders are realized based on signal-light induced plasmonic-nanocavity-modes shift in a planar plasmonic microstructure covered with a nonlinear nanocomposite layer, which can be directly integrated into plasmonic circuits. Tremendous nonlinear enhancement is obtained for the nanocomposite cover layer, attributed to resonant excitation, slow light effect, as well as field enhancement effect provided by the plasmonic nanocavity. The feature size of the device is <15 μm, which is reduced by three orders of magnitude compared with previous reports. The operating threshold power is determined to be 300 μW (corresponding to a threshold intensity of 7.8 MW/cm2), which is reduced by two orders of magnitude compared with previous reports. The intensity contrast ratio between two output logic states, “1” and “0,” is larger than 27 dB, which is among the highest values reported to date. Our work is the first to experimentally realize on-chip half- and full-adders based on nonlinear plasmonic nanocavities having an ultrasmall feature size, ultralow threshold power, and high intensity contrast ratio simultaneously. This work not only provides a platform for the study of nonlinear optics, but also paves a way to realize ultrahigh-speed signal computing chips.

Low-dimensional materials-based field-effect transistors

As Moores law predicted, field-effect transistors (FETs) have been decreasing in size for several decades. In the process, these devices have suffered considerably from short-channel effects and surface instabilities. Low-dimensional materials, such as 0D quantum dots, 1D nanowires and nanotubes, and 2D nanosheets, would be helpful in the device downscaling process while also enhancing device performance, and have therefore been widely applied in many recently designed FETs. Since the 1990s, more than five million studies related to low-dimensional materials-based FETs have been published. In this article, a universal framework is provided to describe the recent progress in this advanced field and it includes discussions of novel materials, new device configurations and the wide variety of device applications.