Feixia Yu

Modeling of thermal behavior in SOI structures

Several physics-based analytical steady-state heat flow models for silicon-on-insulator (SOI) devices are presented, offering approaches at different levels of accuracy and efficiency for prediction of temperature profiles induced by power dissipated in SOI MOSFETs. The approaches are verified with the rigorous device simulation based on the energy transport model coupled with the heat flow equation. The models describe the one-dimensional temperature profile in the silicon film of SOI structure and two-dimensional heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to (or gain from) interconnects, and heat exchanges between devices. These models are applied to investigate thermal behavior in single SOI devices and two-device SOI structures.

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Abstract Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.

High performance SOI DTMOS using a retrograde base with a low impurity surface channel

This paper presents a simulation-based investigation on 0.13 /spl mu/m SOI dynamic threshold MOS (DTMOS) structures with uniform and retrograde base profiles. The base of the retrograde SOI DTMOS is split into a low impurity surface channel and a heavily doped body. The low impurity channel is able to provide high channel mobility, and the heavily doped body enhances the body bias effect to take full advantage of the DTMOS function. In addition, the heavily doped body is responsible for lowering body and off currents, and can also effectively suppress short-channel effects.

Thermal modeling of silicon-on-insulator current mirrors

An analytical approach to thermal modeling of SOI circuits is presented, accounting for heat exchanges among devices and heat loss from the Si film, polylines and interconnects through BOX/FOX to the substrate. The approach was applied to SOI current mirrors to study temperature profiles in devices, polylines and interconnects. Electrothermal simulation was also performed, using the developed model and the thermal circuit in BSIMSOI.

Heat flow in SOI current mirrors

An analytical heat flow model, accounting for heat exchanges among devices via interconnect/poly lines and heat loss to oxide is developed and applied to study heat flow in SOI current mirror structures. An SOI nMOS current mirror illustrates the thermal coupling and heat flow through the interconnect. The interconnect provides an efficient heat loss medium for the SOI circuit.

Heat flow models for silicon-on-insulator structures

Self-heating has become a critical issue for modeling and reliability prediction of SOI devices and circuits due to the low thermal conductive BOX. Accurate and efficient thermal models for SOI MOSFETs and interconnects are therefore very much needed. This study presents several analytical steady-state SOI heat flow models at different levels of accuracy and efficiency for prediction of temperature profiles. The models describe the ID SOI silicon-film temperature profiles and 2D heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to interconnects, and heat exchanges between devices. These models are applied to investigated thermal behavior in single-devices and 2-device SOI structures. Results are verified with the rigorous device simulation.

Nonisothermal Effects in SOI CMOS Analog Integrated Circuits Based on Electrothermal Simulation

An analytical approach to electrothermal simulation of SOI integrated circuits is presented, accounting for large temperature gradients in the devices. Electrothermal simulations of SOI analog circuits in Spice coupled with the nonisothermal approach are performed and compared with the isothermal BSIMSOI thermal circuit. Heat flow, thermal coupling and self-heating effects in some SOI analog integrated circuits are examined. Nonisothermal effects on some electrical properties of analog circuits are also briefly discussed

Electrothermal Modeling of an SOI Differential Amplifier

The analytical thermal models developed recently for SOI MOSFETs and interconnects [1,2] are applied in this work to study heat flow and self-heating effects in an SOI circuit. The models have been verified with 2D device and 3D interconnect simulations [1,2]. Unlike the isothermal BSIMSOI thermal circuit [3], the device thermal model [1] accounts for temperature variation on the Si island. With the interconnect thermal model [2] incorporated into the device thermal model, the approach can properly describe heat exchanges in SOI circuit structure [2]. The analytical device thermal model [1] can also accurately describe heat flow in SOI structure with multi devices on the same island. Fig. 1 displays the temperature profile on a 2-device silicon island derived from the analytical model compared to a device simulator [4]. Temperatures (Td1, Tg1, Ts, Tg2, and Td2) are assigned to the ends of metal/poly lines. Fig. 1 demonstrates the validity of the device thermal model and illustrates large temperature gradients on the island, indicating that the isolthermal BSIMSOI thermal circuit [3] is oversimplified. Electrothermal simulation of an SOI current mirror given in Fig. 2(a) was performed in SPICE with Si island termperature derived from the analytical model compared to the BSIMSOI thermal circuit. Temperatures at the ends of metal lines, Tref, TM,2d and Tss, are fixed. Because Iref is constnat in M1, ∆Vds1 in Fig. 2(b) indicates the strength of thermal coupling between M1 and M2 [5]. Due to the constant device temperature in BSIMSOI, source/drain temperature using BSIMSOI is considerably higher than the realistic temperature, and thermal coupling resulting from the BSIMSOI thermal circuit compared to the model taking into account the large temperature gradients is substantially overestimated. The analytical approach is applied to an SOI differential amplifier shown in Fig. 3. Drain currents of the current source, Mp3, and differential pair, Mp1-Mp2, derived from 3 different approaches are displayed in Fig. 4 as functions of Vin1. Drain current neglecting slef-heating is overestimated by 10%-20% for -1V < Vin1 < 1V. Temperature profiles along FOX and the Si island for MN1 and MN2 are given in Fig. 5 at Vin1 = −1V and −0.5V. Because of the negative values of Vin1, most of power is dissipated in MN1, as revealed in Fig. 4 where Idp1 Idp2 at Vin1 = −1V. A high peak temperature in MN1 derived from the analytical thermal model is thus observed. The BSIMSOI circuit [3] however gives a constant temperature (considerably lower than the peak temperature predicted by the analytical model) for these 2 devices (MN1 and MN1) on the same island. Average channel temperatures of MN1 and MN2, derived from the analytical approach, are displayed in Fig. 6 as functions of Vin1, compared to device temperatures derived from the BSIMSOI circuit. Results from these 2 approaches are only close to each other at Vin1 ≈ 0 when 2 devices dissipate nearly equal power. Temperature profiles in Figs. 1 and 5 provide some useful information. The anlytical approch accounting for temperature variation on the island is able to accurately predict the large peak temperature. Constant temperature given by BSIMSOI is substantally lower than the realistic peak temperature and higher than source/drain temperature. Temperature predicted by BSIMSOI will lead to erroneous analysis of device reliability and heat flow from devices to interconnects. In addition, device temperature predicted by BSIMSOI at large Vin1 is relatively large in one device (MN2) and small in the other (MN1) in the active load, compared to the average channel temperatures derived from the analytical approach. Heat flow through interconnects and temperature profiles in pMOSs will be further examined in detail. Acknowledgement This work was partially supported by NSF, grant DMR-0121146.