Felipe Restrepo-Calle

A Novel Co-Design Approach for Soft Errors Mitigation in Embedded Systems

There is an increasing concern about the mitigation of radiation effects in embedded systems. This fact is demanding new flexible design methodologies and tools that allow dealing with design constraints and dependability requirements at the same time. This paper presents a novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques. A hardening infrastructure, which facilitates the design space exploration and the trade-offs analyses, has been developed to support this fault tolerance co-design approach. The advantages of our proposal are illustrated by means of a case study.

Compiler-Directed Soft Error Mitigation for Embedded Systems

The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. The methodology is supported by an infrastructure that permits to easily combine hardware/software soft errors mitigation techniques in order to best satisfy both usual design constraints and dependability requirements. It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic generation of protected source code (hardened code). Two case studies are presented. In the first one, several software-based mitigation techniques are implemented and evaluated showing the flexibility of the infrastructure. In the second one, a customized fault tolerant embedded system is designed by combining selective protection on both hardware and software. Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. Among the developed software-based mitigation techniques, a novel selective version of the well known SWIFT-R is presented.

Fault tolerant embedded systems design by multi-objective optimization

The design of fault tolerant systems is gaining importance in large domains of embedded applications where design constrains are as important as reliability. New software techniques, based on selective application of redundancy, have shown remarkable fault coverage with reduced costs and overheads. However, the large number of different solutions provided by these techniques, and the costly process to assess their reliability, make the design space exploration a very difficult and time-consuming task. This paper proposes the integration of a multi-objective optimization tool with a software hardening environment to perform an automatic design space exploration in the search for the best trade-offs between reliability, cost, and performance. The first tool is commanded by a genetic algorithm which can simultaneously fulfill many design goals thanks to the use of the NSGA-II multi-objective algorithm. The second is a compiler-based infrastructure that automatically produces selective protected (hardened) versions of the software and generates accurate overhead reports and fault coverage estimations. The advantages of our proposal are illustrated by means of a complex and detailed case study involving a typical embedded application, the AES (Advanced Encryption Standard).

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

Selective SWIFT-R

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

Soft core based embedded systems in critical aerospace applications

There is an increasing interest in the aerospace industry to reduce the cost of the systems by means of using Commercial Off The Shelf (COTS) devices. The engineering of novel microsatellites and nanosatellites are clear examples of this new trend. However, the use of sub-micron technologies has led to greater sensitivity of these devices to radiation-induced transient faults, limiting the exploitation of this approach in critical systems. This paper presents an innovative application of soft-core microprocessor based embedded systems, to design dependable and reduced-cost critical systems with COTS reconfigurable devices (flash based FPGAs). To make this possible, it is necessary to fine-tune the protection strategy by combining selectively fault mitigation techniques based on hardware or software. In this way, the resultant system not only fulfills both the design constraints and the dependability requirements, but also avoids the cost provoked by excessive use of protection mechanisms. A case study is presented in which the design space exploration between hardware and software protection techniques permits to find the best trade-offs among performance, reliability, memory size and hardware cost in a dependable subsystem.

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the co-design of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.

Finding relationships between socio-technical aspects and personality traits by mining developer e-mails

Personality traits influence most, if not all, of the human activities, from those as natural as the way people walk, talk, dress and write to those most complex as the way they interact with others. Most importantly, personality influences the way people make decisions including, in the case of developers, the criteria they consider when selecting a software project they want to participate. Most of the works that study the influence of social, technical and human factors in software development projects have been focused on the impact of communications in software quality. For instance, on identifying predictors to detect files that may contain bugs before releasing an enhanced version of a software product. Only a few of these works focus on the analysis of personality traits of developers with commit permissions (committers) in Free/Libre and Open-Source Software projects and their relationship with the software artifacts they interact with. This paper presents an approach, based on the automatic recognition of personality traits from e-mails sent by committers in FLOSS projects, to uncover relationships between the social and technical aspects that occur during the software development process. Our experimental results suggest the existence of some relationships among personality traits projected by the committers through their e-mails and the social (communication) and technical activities they undertake. This work is a preliminary study aimed at supporting the setting up of efficient work teams in software development projects based on an appropriate mix of stakeholders taking into account their personality traits.

A co-design approach for SET mitigation in embedded systems

We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with respect to SET effects. The advantages of the proposed approach are demonstrated by means of a case study.