Fenghao Mu

Self-tested self-synchronization circuit for mesochronous clocking

In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-/spl mu/m CMOS. Comparison is made between STSS-1 and STSS-3.

Analysis and optimization of a uniform long wire and driver

An analytical delay model of a uniform wire and driver, based on a combination of a switch-level model and Elmore delay is developed for the on-chip interconnections. The model is utilized for the optimization of delay, power, area, or combinations thereof, subject to different constraints. A linear relation between wire width and transistor widths is proposed, which leads to closed-form solutions to the optimization problems. These solutions are valid also for a multistage uniform wire and driver and are easily used in practical design. The solutions are compared to SPICE simulated results, using practical process parameters. Results show that the root of mean square (rms) errors of delay and power between SPICE simulation and the proposed method are around 3%.

Self-tested self-synchronization by a two-phase input port

In high speed large systems, global clocking is used to protect clocked I/O from data read failure due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method implemented by a two-phase input port for parallel data transfer between blocks. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput; less power consumption in clock distribution; no constraints on clock skew and system scale; easy in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, robust parallel data transfer between blocks with arbitrary local clock phases is achieved and the problem of global synchronization is avoided in designing high performance ULSI.

Digital multiphase clock/pattern generator

In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz/spl times/32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed.

Vector transfer by self-tested self-synchronization for parallel systems

Communications between processing elements (PEs)in very large scale parallel systems become more challenging as the function and speed of the PEs improve continuously. Clocked I/O ports may malfunction if data read failure occurs due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput, less power consumption in clock distribution, no constraints on clock skew and system scale, easy in design, less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, a robust vector transfer between PEs with arbitrary clock phases is achieved and the headache problem of the global synchronization is avoided.

A layout-based schematic method for very high-speed CMOS cell design

In very high-speed CMOS cell design, the result of schematic simulation is inaccurate because of missing parasitic components, such as diodes and parasitic capacitances. Designer cannot pass enough information to the simulator by conventional transistor symbols, therefore, simulation error occurs. In this paper, we address a layout-based schematic (LBS) method for high-speed CMOS cell design. In this method, we introduce several types of MOS transistors and estimate parasitic wire capacitances by using layout knowledge. The simulation results show that the difference between LBS and real layout is much smaller, less than 3% in rise time, compared to in the worst case of up to 65% in the original schematic. This method can be applied to both digital and analog circuits and it is helpful for layout automation. Time and cost will be reduced in high-speed circuit design.

Efficient high-speed CMOS design by layout based schematic method

As the diffusion area and the wire capacitance worsen the circuit performance in very high speed CMOS design, the results between schematic and layout differ from each other because of missing parasitic components in the schematic. We address a layout based schematic (LBS) method for high speed CMOS cell design. In our method, we introduce different types of MOS transistors and a wire capacitance estimation method, based on layout knowledge. The simulation results at very high speed show that the difference between LBS and real circuit layout is much smaller, less than 3 percent in rise time, compared to the difference in the worst case up to 65 percent in original schematic. The result of LBS is reliable and easy to be optimized during the schematic procedure. It will reduce the design time and cost in high speed circuit design. We also believe that the LBS is more convenient to be translated into the real layout than the original schematic.

High speed interface for system-on-chip design by self-tested self-synchronization

Global synchronization has been commonly used to protect clocked I/O from data read failure due to metastability. For future high performance system-on-chip design, global synchronization is more difficult as both frequency and chip size increase quickly. This paper addresses a mesochronous clocking (MC) strategy which can be implemented with three self-tested self-synchronization (STSS) methods for parallel data transfer between processing elements (PEs). Compared with global synchronization, MC has many advantages: lower process cost; less power dissipation in clock distribution; no limit in system scale; less delay in long distance data transfer; more simplicity and flexibility in design. The STSS implementations are also very simple and robust, and the metastability in data read is avoided because STSS is completely insensitive to both clock skew and data delay.

Self-synchronized vector transfer for high speed parallel systems

Communications between processing elements (PEs) in high speed parallel systems become a bottleneck as the function and speed of the PEs improve continuously. Clocked I/O ports in PEs may malfunction if data read failure occurs due to clock skew. To reduce the clock skew, global clock distribution is utilized, however it seems to be more difficult to use this for high speed parallel systems in the future. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. This method has these features: high data throughput; low power consumption; no constraints on clock skew and system scale; flexibility in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. Using a jitter injected test signal, robust vector transfer between PEs with arbitrary clock phases is achieved without global synchronization.

A digital clock generator for an ATM switch implemented with multiphase clock

A new digital clock generator using multiphase clock to create a system clock is presented. Its main features are: less sensitivity to noise; wider frequency range; digital design method. The clock generator is used in an ATM switch which needs a clock frequency of 376MHz (622MHz×32/53). The maximum time error is half of the phase difference in multiphase clock.