Fengqi Yu

A high output swing current-steering DAC using voltage controlled current source

As the supply voltage decreasing to near 1V, the output swing of the CS-DAC (current-steering digital-to-analogue converter) is limited by the minimum biasing voltage of the current source array, which is approximately 0.4V. This voltage takes one-third of the 1.2V power supply, which makes the single-ended CS-DAC not practical. To eliminate the output swing limitation, a voltage-controlled current source (VCCS) is proposed to realize high-swing single-ended voltage output for CS-DAC. The VCCS has the same input voltage as the biasing voltage. It generates a matching output current to make the minimum output voltage of the single-ended CS-DAC be able to reach the ground. The VCCS adopts a cascode structure in the output path, thus its performance is independent of DAC output changes. Careful matching is made inside VCCS, as well as between VCCS and DAC. Consequently, this design is robust to the process, supply voltage, and temperature (PVT) variations. The proposed CS-DAC, implemented by 180-nm CMOS technology, has a 1V output swing under 1.251.5V power supply at 25C temperature. For all PVT variation corners, the measured minimum DAC output voltage, designed as 0.11V, varies between 0.05V and 0.113V. The measured DNL and INL are normally less than 0.2 LSB and 0.5 LSB, respectively. The measured slewing time for rising and falling step input are 80ns and 90ns, respectively. The measured total power consumption is 1.5mW.

An auto-calibration technique for BJT-based CMOS temperature sensors

To obtain high accuracy, CMOS temperature sensors need to be calibrated. The current available calibration techniques are manual ones. They are time-consuming and expensive. They are not suitable for chip mass production. To solve the problem, we present an individual and automatic calibration technique for BJT-based CMOS temperature sensors. It is an automatic voltage calibration using the trimming circuit based on the successive-approximation algorithm. Experimental results show that after a 2-second auto-calibration, the sensor can achieve an accuracy of −1 °C∼ 1.5 °C from −40 °C to 100 °C.

Analysis of the residual error due to mechanical stress in BJT-based CMOS temperature sensors

It is widely known that the inaccuracy of BJT-based CMOS temperature sensors is higher at high temperature range, which greatly limits their application. In this paper, the characteristic of the error after calibration is analyzed. Through the experiments, we discover that the cause of this problem is not circuit related, instead it is process related, which is the mechanical stress generated during manufacturing and packaging. Experimental results show that an accuracy of −0.5 ~ 2 °C can be obtained for the calibrated non-epoxy sensors from −40 °C to 120 °C.

A novel high-speed divide-by-3/4 prescaler

A novel extended true single-phase clock-based (ETSPC) divide-by-3/4 prescaler is presented. Instead of the conventional technologies (i.e. transmission gates, logic gates), by using the pass transistor logic circuit, only two transistor are needed to realized the mode selection control. The operation speed is improved by reduction of the critical path delay between the ETSCP flip-flops. Since the number of additional transistors compared with the counter for divider is only two, the low power consumption can be achieved. Simulation results in a standard 180nm CMOS process show that the operation speed of the proposed divide-by-3/4 prescaler is 15.9%∼103% faster than the conventional divide-by-3/4 prescaler.

A novel shift-multiply framework for one-dimensional chaotic map

This paper introduces a shift-multiply framework to generate one-dimensional (1-D) chaotic maps using a combination of two 1-D chaotic maps (called seed maps). On the basis of conventional 1-D chaotic map, its iteration algorithm is improved which enhances the ability of anti-dawning. Simulations show that the proposed chaotic maps have more parameters and greater chaotic range than current seed maps. It also has good initial-value sensitivity, correlation, and balance performance. It is a good candidate in the DSSS (direct sequence spread spectrum) underwater communication system.

A Doppler shift estimation algorithm with low computational complexity for underwater acoustic communication

In underwater acoustic communication system, carrier synchronization and symbol synchronization are adversely affected by Doppler Effect, due to relative motion of the transmitter and receiver. This paper presents a novel Doppler shift factor estimation algorithm. That is the joint estimation of frequency spectrum using FFT and technique of ambiguity function. First the search range of ambiguity function is determined in a small range by using FFT spectrum analysis of the continuous wave (CW) signal. Then Doppler shift factors estimated by using ambiguity function for linear frequency modulated (LFM) signal. Simulation results show that a small number of corrugators can achieve the required Doppler shift accuracy when SNR is greater than -5dB. Therefore the hardware complexity is dramatically reduced.