Fernando Guarin

The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in the system was characterized by secondary ion mass spectroscopy (SIMS) and then correlated to a number of important technological device parameters. The threshold voltages of thin (3.5 nm) and thick (6.8 nm) field-effect transistors (FETs) were measured, and an increase in interface trap density with increasing fluorine content was identified. An increase in oxide thickness and improvement in hot-carrier immunity were observed. Little change to oxide dielectric integrity was noted, but the negative bias threshold instability (NBTI) shift was improved with the introduction of fluorine. These data indicate that benefits may be obtained by introducing fluorine into the p-type FET (PFET), but that the increase in interface traps makes fluorine in the n-type FET (NFET) less attractive from a technological perspective. These data are in agreement with a previously proposed mechanism whereby fluorine removes hydrogen-related sites from the oxide.

NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

In this work the reliability of a 0.35 /spl mu/m p+ poly-gate pMOSFET CMOS technology under conductive channel hot carrier conditions is investigated. It is found that at any bias and temperature condition applied, the degradation of sufficiently short channel length (Leff/spl sime/0.14 um) devices results in a reduction in drive current due to the impact of donor type interface trap generation and positive charge formation during the stress. At these dimensions the degradation is controlled by a contribution of both Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) mechanism. We will show the role that each of these two mechanisms play in determining the shift of typical device parameters. A methodology to decouple the two effects is also provided allowing to quantify each contribution separately at any bias and temperature condition. A conductive CHC model that takes into account the impact of both mechanisms to the device lifetime at the worst observed degradation condition (Vg=Vd) is also discussed.

Foundation of rf CMOS and SiGe BiCMOS technologies

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

Role of E-E scattering in the enhancement of channel hot carrier degradation of deep-submicron NMOSFETs at high V/sub GS/ conditions

It has been reported in the literature that in deep-submicron nMOSFETs, the worst channel hot carrier (CHC) degradation is not near the peak substrate current (as predicted by the lucky electron model), but at the V/sub GS/=V/sub DS/ bias condition. We propose a new CHC model based on an electron-electron scattering-induced hot carrier (HC) mechanism, that explains the worsening of the HC damage at high VGs and agrees well with the HC lifetime measured over the moderate to high gate voltage range and a wide L/sub EFF/ range. The predicted quadratic source current dependence of HC lifetime at mid V/sub GS//V/sub DS/, evolving into a cubic dependence at high V/sub GS//V/sub DS/, matches well the observed behavior.

Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.

SiGe HBT performance and reliability trends through f/sub T/ of 350 GHz

We discuss the SiGe HBT structural changes required for very high performance. The increase in collector concentration, affecting current density and avalanche current, appears to be the most fundamental concern for reliability. In device design, a narrow emitter and reduced poly-single-crystal interfacial oxide are important elements in minimizing device parameter shifts. From the application point of view, avalanche hot-carriers appear to present new constraints, which may be managed through limiting voltage (to 1.5/spl times/-2/spl times/ BV/sub CEO/), or through circuit designs robust to base current parameter shifts.

Self-heating and its implications on hot carrier reliability evaluations

Device level Self-Heating (SH) is becoming a limiting factor during traditional DC Hot Carrier stresses in bulk and SOI technologies. Consideration is given to device layout and design for Self-Heating minimization during HCI stress in SOI technologies, the effect of SH on activation energy (Ea) and the SH induced enhancement to degradation. Applying a methodology for SH temperature correction of extracted device lifetime, correlation is established between DC device level stress and AC device stress using a specially designed ring oscillator.

BAND-EDGE PHOTOLUMINESCENCE FROM PSEUDOMORPHIC SI0.96SN0.04 ALLOY

Band‐edge related photoluminescence from a strained Si0.96Sn0.04 alloy grown by molecular beam epitaxy on Si(100) substrate has been seen for the first time. We report band‐edge related photoluminescence from a compressively strained pseudomorphic Si0.96Sn0.04 alloy. The luminescence observed consisted of two dominant features, a well‐resolved band‐edge luminescence consisting of a no‐phonon and a transverse optical phonon replica, and a deep‐level broad luminescence peak around 770 meV. The band‐edge feature is attributed to a no‐phonon free excitonic recombination in the binary alloy and exhibits a near linear power dependence. We also observe a red shift of the energy gap of Si0.96Sn0.04 alloy with respect to Si, which corresponds to the bulk alloy effect.

High-

Recently, negative bias temperature instability (NBTI) enhanced by local self-heating has been proposed as a mechanism for high-Vg PFET ¿hot-carrier¿ degradation. This is based on the idea that the effective temperature for NBTI is increased in the drain region due to a very localized self-heating effect reported in the literature by Pop and others. Our PFET dc stress data are consistent with local self-heating activated NBTI at high Vg , but at mid Vg, we observed similar behavior to typical NFET hot carriers, i.e., energy-driven hot carrier (EDHC). If self-heating is involved with the PFET high-Vg dc degradation, the question of ac behavior naturally arises. Our PFET ring-oscillator stress results demonstrate that the high-VGS PFET hot carrier dominant under dc stress does not significantly contribute under typical CMOS switching conditions, whereas the mid-VGS hot carrier does. This supports the idea that the predominant damage mechanism involved at high VGS is NBTI enhanced by local self-heating with a thermal time constant longer than a few hundred picoseconds.